62 results about "Adaptive logic" patented technology

In a memory system having multiple erase blocks in multiple planes, a selected number of erase blocks are programmed together as an adaptive metablock. The number of erase blocks in an adaptive metablock is chosen according to the data to be programmed. Logical address space is divided into logical groups, a logical group having the same size as one erase block. Adaptive logical blocks are formed from logical groups. One adaptive logical block is stored in one adaptive metablock.

A nonvolatile memory is organized into blocks as erase units and physical pages as read / write units. A host addresses data by logical pages, which are storable in corresponding physical pages. Groups of logical pages may be further aggregated into logical groups as addressing units. The memory writes host data in either first or second write streams, writing to respective blocks either logical-group by logical-group or logical-page by logical-page in order to reduce the size of logical-to-physical-address maps that are cached in a controller random-access memory (RAM). A group-level map may be used to track logical groups. A page-level map may be used to track logical pages. Only one block at a time needs be open in the second stream to accept logical pages from multiple logical groups that are active. Garbage collection is performed on the blocks from each write stream independently without data copying between the two streams.

The invention discloses a field programmable gate array (FPGA) based automatic power control circuit and method. The loop-locked power control circuit comprises a power amplification circuit, a coupling circuit, a detector circuit, an ARM circuit and an FPGA circuit. An output radio frequency signal of the power amplification circuit is coupled by the coupling circuit and then is output to the detector circuit, and the detector circuit samples the radio frequency signal and outputs an obtained sampling signal to the ARM circuit; and the ARM circuit compares a power level obtained through conversion of the sampling signal with an original power level, calculates to obtain an adjustment signal of the FPGA circuit and gives the adjustment signal to the PFGA circuit, and controls the PFGA circuit to output a required radio frequency signal to the input end of the power amplification circuit. According to the FPGA based automatic power control circuit and method, an electronic speed control attenuation circuit is saved, and data collected by the ARM is directly fed back to the FPGA circuit, thereby controlling the output power, improving control accuracy and speed, simplifying circuit design and increasing initial control depth of an adaptive logic circuit (ALC).

A control system for a gas turbine engine including a power turbine is disclosed. The control system may include a control module to receive engine operating goals and an estimated current engine state, wherein the estimated current engine state is produced by a model-based estimation module using a bandwidth signal produced by an adaptation logic module. The control module is operative to determine fuel flow, inlet guide vane schedules and stability bleed schedules based at least in part on the received engine operating goals and the estimated current engine state, and to send signals to a gas generator of the gas turbine engine in order to control the gas generator according to the determined fuel flow, inlet guide vane schedules and stability bleed schedules.

Adaptive profiling for performance analysis of a computer system controls one or more agents to monitor a plurality of events occurring in a target computer system based on an adaptive logic. Collected data may be filtered and analyzed to determine one or more contributor events that attribute to performance of the target computer system. One or more patterns are observed or detected in said collected data, behavior of said one or more agents are adjusted based on said detected one or more patterns. The adaptive logic may be further reconfigured based on said detected one or more patterns.

The invention discloses an adaptive network voltage feed-forward compensation method for a grid-connected inverter and belongs to the field of current control of the grid-connected inverter (including an inverter and a rectifier). The method comprises the following steps that the network voltage of a point of common coupling is sampled and the voltage is taken as an input signal for adaptive network voltage feed-forward compensation of the grid-connected inverter, the input signal generates one group of output signals through one group of parallel band-pass filters at the harmonic frequency, and independent output signals in the group of output signals are added to generate a voltage signal used for feed-forward compensation; and meanwhile, resonance detection is carried out on the independent output signals, and when the amplitude of one output signal is suddenly increased, the related output signal is eliminated from the voltage signal used for feed-forward compensation according to the adaptive logic. The method has the advantages of strong adaptability for large-range varying network impedance, excellent grid-side current quality and convenience for design.

The invention provides a programmable signal processing unit based on a function generating unit. According to the programmable signal processing unit, the function generating unit which has an logical operation function and a data storage function is adopted and is connected with a flexible multiplexer in a matched mode, as a result, the programmable signal processing unit can be used for storing configuration data to achieve independent self-adaptive logic operation and storing user data to achieve reading / writing operation of a fine-grained data memory on one hand and can achieve mixed operation of the self-adaptive logic operation and the reading / writing operation of the fine-grained data memory on the other hand, and therefore the resource use efficiency of a programmable chip is greatly improved.

An enhancement system improves the estimate of noise from a received signal. The system includes a spectrum monitor that divides a portion of the signal at more than one frequency resolution. Adaptation logic derives a noise adaptation factor of the received signal. A plurality of devices tracks the characteristics of an estimated noise in the received signal and modifies multiple noise adaptation rates. Weighting logic applies the modified noise adaptation rates derived from the signal divided at a first frequency resolution to the signal divided at a second frequency resolution.