35results about How to "Improved resistance to single event upset" patented technology

A single-event hardened programmable double data rate register circuit and control method, realize the single-event harden The generating circuit, the data multiplexer and the data holding circuit are used to control the timing of multiple double-redundant interlocking structure registers to realize the double data rate register function in multiple modes. The single particle reinforcement index of the present invention is three orders of magnitude higher than that of traditional registers, and can realize level latches, single data rate edge triggers, reverse edge mode double data rate edge triggers and same edge mode double data rate edges Programmable functions such as flip-flops enable users to have higher flexibility, better timing performance and extremely high anti-single event hardening indicators when using programmable user registers.

The invention belongs to the technical field of D flip-flops, and provides an asynchronous set D flip-flop with the capacity for resisting single event upset. The D flip-flop comprises a clock signal input circuit, a reset signal input circuit, a main latch buffering circuit, an auxiliary latch buffering circuit, a main latch and an auxiliary latch, and the main latch and the auxiliary latch are latches with bimodule redundancy reinforcing. Compared with the prior art, the buffering circuits are additionally arranged before the main latch and the auxiliary latch, the capacity for resisting single event upset of the asynchronous reset D flip-flop is improved, bimodule redundancy reinforcing is carried out on the main latch and the auxiliary latch, namely the main latch and the auxiliary latch are separated into a pull-up PMOS tube and a pull-down NMOS tube redundant to each other in the C2MOS circuits, a feedback loop possibly caused by single particle transient pulse in the auxiliary latch is avoided, the C2MOS circuits in the main latch and the auxiliary latch are improved, control over the circuits by clock signals is achieved through a CMOS transmission gate, and the capacity for resisting single event upset of the asynchronous set D flip-flop is improved further.

The invention is suitable for the technical field of D triggers, and provides a synchronous reset D trigger for preventing single event upset. The D trigger comprises: a clock signal input circuit, a reset signal input circuit, a master latch buffer circuit, a slave latch buffer circuit, a master latch and a slave latch, and both of the master latch and slave latch are dual mode redundancy reinforcement latches. Compared with the prior art, in the synchronous reset D trigger provided by the invention, the buffer circuits are added in front of the master latch and slave latch, so the single event upset ability of the synchronous reset D trigger is improved, dual mode redundancy reinforcement is carried out on the master latch and slave latch, namely the master latch and slave latch are separated to a pull up PMOS tube and a pull down PMOS tube in a C2MOS circuit, which are redundant to each other, therefore a possible feedback circuit caused by single event transient pulses is avoided, the C2MOS circuits in the circuits of the master latch and slave latch are improved, clock signals control the circuits through SMOS transmission rates, and the single event upset ability of the synchronous reset D trigger is further improved.

The invention discloses an anti-single event upset and anti-single event transient settable reset scanning structure D trigger, for the purpose of solving the problems of not high anti-single event upset capability and not high anti-single event transient capability. The settable reset scanning structure D trigger provided by the invention is composed of a buffer circuit, a scanning control buffer circuit, a setting buffer circuit, a reset buffer circuit, a clock circuit, a master latch register, a slave latch register and an output buffer circuit. The master latch register and the slave latch register are latch registers with redundancy reinforcement. The master latch register and the slave latch register are connected in series and are both connected with the clock circuit, the setting buffer circuit and the rest buffer circuit. The master latch register is also connected with the buffer circuit and the scanning control buffer circuit. The slave latch register is also connected with the output buffer circuit. According to the invention, mutually redundant C<2>MOS circuits are separated from the master latch register and the slave latch register so that the anti-single event upset capability is improved. The buffer circuit enables no errors to be generated under a single event transient pulse which lasts for quite a long time. A dual-mode redundancy pathway further enhances the anti-single event upset capability.

The invention discloses a D trigger provided with a scanning structure and resisting single event upset, and aims to improve the single event upset resistance of the D trigger provided with the scanning structure. The D trigger comprises a clock circuit, a scanning control buffer circuit, a main latch, a slave latch, a first phase inverter circuit and a second phase inverter circuit, wherein the main latch comprises 16 PMOS (P-channel Metal Oxide Semiconductor) tubes and 16 NMOS (N-Mental-Oxide-Semiconductor) tubes; the slave latch comprises 10 PMOS tubes and 10 NMOS tubes; both the main latch and the slave latch adopt bimodule redundant reinforcement; and in the main latch and the slave latch, C2MOS circuits are improved, that is, a pull-up circuit and a pull-down circuit in redundant relation in each C2MOS circuit are separated. The D trigger has strong single event upset resistance, is suitable for standard cell library for a reinforced integrated circuit resisting single event upset, and is used in the fields of aviation, aerospace, and the like.

The invention discloses a single event upset resistant settable and resettable scan structure D flip-flop, aiming at improving the single event upset resistance of the single event upset resistant settable and resettable scan structure D flip-flop. The scan structure D flip-flop is composed of a clock circuit, a scanning control buffer circuit, a resetting buffer circuit, a master latch, a slave latch and an output buffer circuit, wherein the master latch is composed of 20 PMOS (P-channel Metal Oxide Semiconductor) FETs (Field Effect Transistors) and 20 NMOS (N-channel Metal Oxide Semiconductor) FETs, the slave latch is composed of 10 PMOS FETs and 10 NMOS FETs, duplication redundant reinforcement is performed on both the master latch and the slave latch, and the C2MOS (Clocked Complementary Metal Oxide Semiconductor) circuit structures in the master latch and the slave latch are improved, i.e. a pull-up circuit and a pull-down circuit in the mutually redundant C2MOS circuits are separated. The scan structure D flip-flop disclosed by the invention has strong single event upset resistance, is suitable for a standard cell library of a single event upset resistance reinforced integrated circuit, and is applied to the fields of aviation, aerospace and the like.

The invention discloses an anti-single-event-upset latch register with a low delay-power product. By use of a novel cross coupling structure capable of isolating an upset state, recovery of the upset state is accelerated through design of a reasonable negative feedback passage. In case of a data transparent mode, negative feedback is cut off so as to improve the writing speed of a circuit. A simulation result under a 40nm CMOS technology shows that the critical charge ratio of the latch register provided by the invention is more than 50 times higher than that of a conventional latch register. The delay-power product is only 0.0035fs*J, and the propagation time delay under the non-loaded condition is only 23.3ps, which is lower than that of a same-type latch register.