D trigger resistant to single event upset
An anti-single event and flip-flop technology, applied in the direction of pulse generation, electrical components, electric pulse generation, etc., can solve the problem that the D flip-flop cannot meet the anti-single event flipping and other problems
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[0026] figure 1 It is a logical structure diagram of a D flip-flop using a master-slave two-level Latch structure.
[0027] Both the ordinary D flip-flop and the D flip-flop of the present invention are composed of a master latch (Latch) and a slave Latch connected in series, and the structure of the master Latch and the slave Latch are exactly the same.
[0028] figure 2 It is a logic structure diagram of a master-slave two-level Latch and a Latch core in a common D flip-flop in the background technology.
[0029] The main Latch or slave Latch of a common D flip-flop is composed of an input inverter with clock control, a feedback inverter with clock control and an inverter. The core of Latch is composed of two inverters connected end to end.
[0030] image 3 (a) is the third inverter, which is composed of a PMOS transistor and an NMOS transistor, wherein the drains of the PMOS transistor and the NMOS transistor are connected to form the output of the inverter, and the ...
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