The invention provides a method for achieving a variable bit width division method through an FPGA, and the method comprises the steps: S1, decomposing a divisor into n segments, calling a basic bit division unit, dividing a decomposed first segment by a dividend, and obtaining a first quotient and a first remainder of the first segment; S2, combining the first remainder with a second segment divisor, and continuously dividing by the dividend to obtain a second quotient and a second remainder of the second segment; splicing the second remainder and the third segment divisor, and dividing the second remainder and the third segment divisor by the dividend to obtain a third quotient and a third remainder of the third segment; and S3, repeating the process until the nth quotient and the nth remainder are obtained, the nth remainder being the remainder obtained by the variable bit width division method, the splicing of the n segments of quotients from the first quotient to the nth quotientbeing the quotient obtained by the variable bit width division method, and ending the operation. According to the method for achieving the variable bit width division method through the FPGA, divisionoperation of any bit width can be achieved, and compared with a traditional method, the shifting division method is greatly improved in speed.