158results about "Paste/ink/powder application resist" patented technology

Processes for controlling ink migration during the formation of printable electronic features. In a preferred aspect, the invention is to a process for forming at least a portion of an electronic feature. The process includes the steps of: (a) providing a first substrate having a first surface; (b) modifying the first surface to form a modified surface; and (c) applying an ink to at least a portion of the modified surface, wherein the modified surface interacts with the ink to inhibit lateral and/or longitudinal migration of the applied ink, and wherein the applied ink forms at least a portion of the electronic feature. In another aspect, the invention is to a process for encouraging electronic ink spreading with a surfactant.

This specification describes techniques for fabricating connections between pairs of components. Each connection includes an array of bumps on a male component, and a matching array of wells filled with bonding material on a female component. The bump/well connections can be spaced with a pitch of less than 100 microns. One application of the invention is the attachment of electronic components to interconnection circuits or circuit assemblies to form electronic modules. The electronic components may be IC chips or high-density interconnect cables. Another application is alignment of optical components. The direct chip attachment techniques are described in the context of fabrication, assembly, test, rework, and cooling of electronic modules employing flip chip components. The preferred method is to fabricate the module on a glass carrier using a release layer so that the carrier can be removed after most of the processing is done.

A process for making a multilayer circuit device having electrically isolated tightly spaced electrical current carrying traces, comprising of providing an insulative substrate having a first side coated with a layer of conductive metal intended to form a ground plane; providing a plurality of seed layer traces of a predetermined width of approximately 25 microns or less separated from each other by a predetermined distance of approximately 25 microns or less on a second side of the insulative substrate, the narrowness of such separation being essentially limited only by characteristics of the photoresist material to be deposited and developed therebetween and to withstand subsequent processing; developing ribs or barriers of photoresist forming vertical walls rising above the spaces separating the seed layer traces and defining valleys or channels thereover; depositing a desired thickness of conductive material over the seed layer traces and in the valleys or channels between the vertical walls; stripping away the resist ribs or barriers to leave conductive traces to be variously used as ground lines, signal lines and power lines; repeating the previous steps to develop a plurality of circuit boards; stacking the several circuit boards and joining them together with layers of insulative material; identifying particular ones of the traces as signal lines and other traces as power lines and/or ground lines; interconnecting at least some of the ground lines on one board to ground lines and/or ground planes on other boards by conductors extending through vias; interconnecting signal lines to signal input and output terminals; and perhaps to signal lines on other boards through vias; and interconnecting power lines to power input and output terminals, and perhaps to power lines on other boards through vias.

A method of fabricating touch panel includes the following steps. A base is provided. A first transparent conductive layer is formed on the base. A first screen printing process is performed to form a first patterned sacrificial layer on the first transparent conductive layer, and the first patterned sacrificial layer is used to pattern the first transparent conductive layer to form a patterned sensing pad layer. A second screen printing process is carried out to form a patterned insulating layer. A second transparent conductive layer is formed on the base. A third screen printing process is performed to form a second patterned sacrificial layer, and the second patterned sacrificial layer is used to pattern the second transparent conductive layer to form a patterned bridge line layer.

Disclosed is a PCB including embedded capacitors and a method of fabricating the same. A dielectric layer is formed using a ceramic material having a high capacitance, thereby assuring that the capacitors each have a high dielectric constant corresponding to the capacitance of a decoupling chip capacitor.

A method of forming a pattern includes forming mark partition walls that correspond to an alignment mark on a substrate before forming the pattern by providing a pattern forming material between partition walls, and providing a liquid material containing an alignment mark forming material between the mark partition walls.

This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths of 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is used to fabricate the interconnection circuits. A polymer base layer is formed on a glass carrier with an intermediate release layer. Alternate layers of metal and dielectric are formed on the base layer, and patterned to create an array of multi-layer interconnection circuits on the glass panel. A thick layer of polymer is deposited on the interconnection circuit, and openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings to form wells filled with solder. After dicing the glass carrier to form separated interconnection circuits, IC chips are stud bumped and assembled using flip chip bonding, wherein the stud bumps on the components are inserted into corresponding wells on the interconnection circuits. The IC chips are tested and reworked to form tested circuit assemblies. Methods for connecting to testers and to other modules and electronic systems are described. Module packaging layers are provided for hermetic sealing and for electromagnetic shielding. A blade server embodiment is also described.

An electronic component with bump electrodes includes a surface-protecting insulating film of adequate thickness and bump elements of adequate height, and allows the occurrence of open defects in the manufacturing process to be appropriately reduced. An electronic component with bump electrodes (X1) includes a substrate (11), electrode pads (12) provided on the substrate (11), an insulating film (13) that has openings (13a) in correspondence with the electrode pads (12) and is laminated and formed on the substrate (11), electroconductive connecting elements (14) provided on the electrode pads (12) in the openings (13a), and bump elements (15) that are in direct contact with the electroconductive connecting elements (14) and project from the openings (13a).

A laminated circuit board with electronic components buried therein comprises a substrate on which a land disposed on one main surface thereof is connected and fixed by solder to an integrated circuit (or the like). A sheet is laminated on the upper surface of the substrate. A filling portion by fluid resin is formed by clearance at the outer periphery of the integrated circuit (or the like). The sheet maintains its shape by woven or non-woven cloth having a hole in which the integrated circuit (or the like) is buried. The woven or non-woven cloth is impregnated with resin having heat fluidity and is thermally compressed. Thus, the electrical and mechanical connections between the laminated circuit board and electronic component can be enhanced in reliability.

Disclosed is a method for forming a pattern which comprises the steps of: (a) providing a substrate having a sacrificial layer made of a first material, partially or totally formed on the substrate; (b) forming pattern grooves, which are free from the first material and have a line width of a first resolution or lower, on the sacrificial layer by using a first means, by which the sacrificial layer is directly processed to form a line; (c) filling the pattern grooves with a second material to a second resolution by using a second means, to form a pattern of the second material on the substrate. A substrate having a pre-pattern formed by the method is also disclosed. The method for forming a pattern provides a high-resolution pattern with little or no waste of the second material, thereby reducing production costs. The method includes use of the first means with a high resolution, such as focused energy beams of laser, combined with the second means with a low resolution, such as ink-jet, and provides a high-resolution pattern with high processing efficiency.

A thin-film pattern forming method that deposits a plurality of thin films on a substrate to form a thin-film pattern, includes: forming a second thin film on the substrate, the second thin film having an affinity for a functional liquid containing a thin-film material that makes up a first thin film; providing lyophobic treatment that makes a surface of the second thin film repellent to the functional liquid; forming a concave portion that defines a pattern shape of the first thin film by removing part of the second thin film; discharging the functional liquid to the concave portion; and forming the first thin film by drying the functional liquid discharged to the concave portion.

Using a dry film resist that is a photosensitive resin, a resin mask layer is formed around electrodes on a substrate. A solder precipitating composition is applied on the substrate, and this solder precipitating composition is heated to precipitate solder on the surface of the electrodes. Subsequently, in removing the resin mask layer, at least one selected from glycol ethers and aminoalcohols is used. Thereby, the resin mask layer is removed after heating process. This makes it possible to easily remove the heat-processed resin mask layer in a short period of time without damaging solder resist and solder bumps on the substrate.