81 results about "Variable bitrate" patented technology

A hybrid audio encoding technique incorporates both ABR, or CBR, and VBR encoding modes. For each audio coding block, after a VBR quantization loop meets the NMR target, a second quantization loop might be called to adaptively control the final bitrate. That is, if the NMR-based quantization loop results in a bitrate that is not within a specified range, then a bitrate-based CBR or ABR quantization loop determines a final bitrate that is within the range and is adaptively determined based on the encoding difficulty of the audio data. Excessive bitrates from use of conventional VBR mode are eliminated, while still providing much more constant perceptual sound quality than use of conventional CBR mode can achieve.

A parallel concatenated low density parity check (LDPC) code having a variable code rate is provided by generating, upon receiving information bits, a first component LDPC code according to the information bits, interleaving the information bits according to a predetermined interleaving rule, and generating a second component LDPC code according to the interleaved information bits. With use of the parallel concatenated LDPC code, a mobile communication system can use a Hybrid Automatic Retransmission Request (HARQ) scheme and an Adaptive Modulation and Coding (AMC) scheme without restriction.

Method for dynamically optimizing bandwidth allocation in a variable bitrate conference environment. Conference means with two or more outputs are provided, where each one can output data at different rates, in order to support two or more endpoints which may have different media rates. Two or more endpoints are connected to these conference means for participating in the conference. Whenever more than one video rate is used by participants during the conference, each set of output rates is selected from all possible combinations of output rates in the conference means, wherein the lowest output rate in each selected set is the entry rate of the endpoint joining the conference at the lowest rate. A Quality Drop Coefficient (QDC) for each endpoint that joins the conference is determined for each selected set, wherein the QDC is computed according to the endpoint entry rate and the highest rate, among the output rates of each selected set, that is lower or equal to said endpoints' entry rate. A Quality Drop Value (QDV) is calculated for each of the selected sets, wherein, preferably, the set of output rates with the lowest QDV is determined as the optimal video rate set to select. The video rate of all the endpoints having a video rate above the highest optimal video rate is reduced to the highest optimal video rate, if required, and the video rate of other endpoints having video rate between two consecutive levels of optimal video rates is reduced to the lowest level among said levels. Whenever a change occurs in either the amount of participating endpoints in the conference or in the declared bit rate capability of the participating endpoints, the video rates of all the outputs are recalculated.

Variable modulation within combined LDPC (Low Density Parity Check) coding and modulation coding systems. A novel approach is presented for variable modulation encoding of LDPC coded symbols. In addition, LDPC encoding, that generates an LDPC variable code rate signal, may also be performed as well. The encoding can generate an LDPC variable code rate and / or modulation signal whose code rate and / or modulation may vary as frequently as on a symbol by symbol basis. Some embodiments employ a common constellation shape for all of the symbols of the signal sequence, yet individual symbols may be mapped according different mappings of the commonly shaped constellation; such an embodiment may be viewed as generating a LDPC variable mapped signal. In general, any one or more of the code rate, constellation shape, or mapping of the individual symbols of a signal sequence may vary as frequently as on a symbol by symbol basis.

The invention relates to a self-adaptive code rate controlling method with low complexity. The controlling method comprises two types of operating modes, namely, variable code rate and fixed code rate; wherein the variable code rate is usually used on non-real time application occasions requiring constant image quality, and the fixed code rate is usually used on real time application occasions requiring constant bandwidth; the method can self-adaptively adjust the quantization step size according to different application occasions and the characteristics of video sources, to achieve reasonable distribution of code rates; simultaneously, variation range limitation on the quantization step size is added, thereby quality jump among continuous images is effectively prevented, smooth transition is realized, and the realization of hardware is convenient.

Efficient front end memory arrangement to support parallel bit node and check node processing in LDPC (Low Density Parity Check) decoders. A novel approach is presented by which the front end design of device capable to decode LDPC coded signals facilitates parallel decoding processing of the LDPC coded signal. The implementation of the front end memory management in conjunction with the implementation of a metric generator operate cooperatively lend themselves for very efficient parallel decoding processing of LDPC coded signals. There are several embodiments by which the front end memory management and the metric generator may be implemented to facilitate this parallel decoding processing of LDPC coded signals. This also allows for the decoding of variable code rate and / or variable modulation signals whose code rate and / or modulation varies as frequently as on a block by block basis (e.g., a block may include a group of symbols within a frame).

A variable code rate adaptive encoding / decoding method using LDDC code is disclosed, in which an input source data is encoded using the LDPC (low density parity check) code defined by a first parity check matrix configured with a plurality of submatrices. The present invention includes the steps of generating a second parity check matrix corresponding to a code rate by reducing a portion of a plurality of submatrices configuring a first parity check matrix according to the code rate to be applied to encoding an input source data and encoding the input source data using the second parity check matrix.

A novel method and apparatus for efficiently coding and decoding data in a data transmission system is described. A concatenated coding scheme is presented that is easily implemented, and that provides acceptable coding performance characteristics for use in data transmission systems. The inventive concatenated channel coding technique is well suited for small or variable size packet data transmission systems. The technique may also be adapted for use in a continuous mode data transmission system. The method and apparatus reduces the complexity, cost, size and power consumption typically associated with the prior art channel coding methods and apparatuses, while still achieving acceptable coding performance. The present invention advantageously performs concatenated channel coding without the necessity of a symbol interleaver. In addition, the present invention is simple to implement and thereby consumes much less space and power that do the prior art approaches. The present invention not only eliminates the need for a symbol interleaver between the outer and inner codes, but it also enjoys a drastically reduced implementation complexity of the inner code Viterbi decoder. The preferred embodiment of the present invention comprises an inner code having short length block codes derived from short constraint length convolutional codes utilizing trellis tailbiting and a decoder comprising four four-state Viterbi decoders having a short corresponding maximum length. The inner code preferably comprises short block codes derived from four-state (i.e., constraint length 3), nonsystematic, punctured and unpunctured convolutional code. One significant advantage of the preferred embodiment of the present concatenated coding technique is that packet data transmission systems can be designed to have variable coding gains and coding rates.

Efficient front end memory arrangement to support parallel bit node and check node processing in LDPC (Low Density Parity Check) decoders. A novel approach is presented by which the front end design of device capable to decode LDPC coded signals facilitates parallel decoding processing of the LDPC coded signal. The implementation of the front end memory management in conjunction with the implementation of a metric generator operate cooperatively lend themselves for very efficient parallel decoding processing of LDPC coded signals. There are several embodiments by which the front end memory management and the metric generator may be implemented to facilitate this parallel decoding processing of LDPC coded signals. This also allows for the decoding of variable code rate and / or variable modulation signals whose code rate and / or modulation varies as frequently as on a block by block basis (e.g., a block may include a group of symbols within a frame).

A novel method and apparatus for efficiently coding and decoding data in a data transmission system is described. A concatenated coding scheme is presented that is easily implemented, and that provides acceptable coding performance characteristics for use in data transmission systems. The inventive concatenated channel coding technique is well suited for small or variable size packet data transmission systems. The technique may also be adapted for use in a continuous mode data transmission system. The method and apparatus reduces the complexity, cost, size and power consumption typically associated with the prior art channel coding methods and apparatuses, while still achieving acceptable coding performance. The present invention advantageously performs concatenated channel coding without the necessity of a symbol interleaver. In addition, the present invention is simple to implement and thereby consumes much less space and power that do the prior art approaches. The present invention not only eliminates the need for a symbol interleaver between the outer and inner codes, but it also enjoys a drastically reduced implementation complexity of the inner code Viterbi decoder. The preferred embodiment of the present invention comprises an inner code having short length block codes derived from short constraint length convolutional codes utilizing trellis tailbiting and a decoder comprising four four-state Viterbi decoders having a short corresponding maximum length. The inner code preferably comprises short block codes derived from four-state (i.e., constraint length 3), nonsystematic, punctured and unpunctured convolutional code. One significant advantage of the preferred embodiment of the present concatenated coding technique is that packet data transmission systems can be designed to have variable coding gains and coding rates.

Iterative metric updating when decoding LDPC (Low Density Parity Check) coded signals and LDPC coded modulation signals. A novel approach is presented for updating the bit metrics employed when performing iterative decoding of LDPC coded signals. This bit metric updating is also applicable to decoding of signals that have been generated using combined LDPC coding and modulation encoding to generate LDPC coded modulation signals. In addition, the bit metric updating is also extendible to decoding of LDPC variable code rate and / or variable modulation signals whose code rate and / or modulation may vary as frequently as on a symbol by symbol basis. By ensuring that the bit metrics are updated during the various iterations of the iterative decoding processing, a higher performance can be achieved than when the bit metrics remain as fixed values during the iterative decoding processing.

Metric calculation design for variable code rate decoding of broadband trellis, TCM (trellis coded modulated), or TTCM (turbo trellis coded modulation). A single design can accommodate a large number of code rates by multiplexing the appropriate paths within the design. By controlling where to scale for any noise of a received symbol within a received signal, this adaptable design may be implemented in a manner that is very efficient in terms of performance, processing requirements (such as multipliers and gates), as well as real estate consumption. In supporting multiple code rates, appropriately selection of the coefficients of the various constellations employed, using the inherent redundancy and symmetry along the I and Q axes, can result in great savings of gates borrowing upon the inherent redundancy contained therein; in addition, no subtraction (but only summing) need be performed when capitalizing on this symmetry.

The present invention refers to a signal concentrator comprising:a parallel to serial conversion device comprising a plurality of parallel inputs and a serial output,a control unit comprising detection means adapted for detecting the activity of said plurality of parallel inputs of said parallel to serial conversion device, indication means adapted for indicating the active parallel inputs to the parallel to serial conversion device and controlling means adapted for setting an operating bitrate of the serial output in function of said activity of said plurality of parallel inputs.