38 results about "Time base generator" patented technology

A network controller having a multiprotocol bus interface adapter coupled between a communication network and a computer bus, the adapter including a predictive time base generator; and a management bus controller adapted to monitor and manage preselected components coupled with one of the communication network and the computer bus. The management bus controller is adapted to employ an Alert Standard Format (ASF) specification protocol, a System Management Bus (SMBus) specification protocol, an Intelligent Platform Management Interface (IPMI) specification protocol, a Simple Network Management Protocol (SNMP), or a combination thereof. The network controller also includes a 10 / 100 / 1000BASE-T IEEE Std. 802.3-compliant transceiver and media access controller coupled with the communication network; a buffer memory coupled with the MAC, wherein the buffer memory includes one of a packet buffer memory, a frame buffer memory, a queue memory, and a combination thereof; and a transmit CPU and a receive CPU coupled with the multiprotocol bus interface adapter and the management bus controller. The network controller can be a single-chip VLSI device in an 0.18 micron CMOS VLSI implementation.

A predictive time base generator having predictive synchronizer and replica delay element coupled with the synchronizer feedback delay loop. The predictive time base generator receives a clock signal delayed by a predetermined clock delay and produces a predictive time signal advanced in time by an amount represented by the replica delay element. The replica delay element can replicate one or both of a predetermined clock delay and a predetermined data delay, substantially nullifying the respective delays in critical signal paths of a device. The replica delay element can include replicas of structure(s) found in an incoming clock path and an outgoing data path, such elements including, for example, voltage level shifters, buffers or data latches, multiplexers, wire element models, and the like. A predictive computer bus interface adapter which incorporates the aforementioned predictive time base generator also is provided. Such a predictive interface adapter can be adapted to be observant of stringent bus protocol timing budgets imposed under the PCI and PCI-X local bus protocol, and to be robust relative to variations in design and fabrication processes, and environmental operating conditions.

A time base generator and method for providing a first clock signal and a second clock signal comprising generating the first clock signal at a first clock frequency, dividing the first clock frequency by a first integer to produce a first auxiliary signal, dividing the second clock signal by a second integer to produce a second auxiliary signal, generating an error signal by individually weighting and comparing cycle durations or phasing of the first and second auxiliary signals, and generating the second clock signal by a voltage-controlled oscillator controlled by the error signal such that two clock signals of slightly different frequencies with defined time or phase delay are provided.

A high-speed signal testing system that includes a digital circuitry for providing a pattern tester with oscilloscope functionality at minimal implementation cost. The digital circuitry includes a time-base generator that provides a high-speed repeating time-base signal. The time-base signal, in conjunction with a sub-sampler and an accumulation memory, allows the system to zoom in on, and analyze portions of, one or more bits of interest in a repeating pattern present on the signal under test. Such portions of interest include rising and falling edges and constant high and low bit values.

To provide two clock signals (CLK1, CLK2) of slightly different frequencies (f1, f2) with defined time or phase delay, the first clock signal (CLK1) is generated at the first clock frequency (f1), the first clock frequency (f1) is divided by a first integer (K1) to produce a first auxiliary signal (CLK11), the second clock signal (CLK2) is divided by a second integer (K2) to produce a second auxiliary signal (CLK21), an error signal (ERR) is generated by individually weighting and comparing the cycle durations or phasing of the first and second auxiliary signals (CLK11, CLK21), and said second clock signal (CLK2) is generated by means of a voltage-controlled oscillator (17) controlled by said error signal (ERR).

A frequency synthesizer for a time base generator of a level measuring device which works according to the radar principle, with at least one first output for output of a first frequency signal, with at least one second output for output of a second frequency signal, and with a reference oscillator for producing a reference frequency signal, the first frequency signal and the second frequency signal having a small difference frequency relative to one another, the first frequency signal being producible by interaction of the reference oscillator with a direct digital synthesizer. The first frequency signal and second frequency signal can be generated with especially low noise by the second frequency signal being derived from the reference oscillator without interconnection of a direct digital synthesizer and the direct digital synthesizer being operated such that only a noise spectrum is produced which is at least partially minimized.

A digital time base generator and method for providing a first clock signal and a second clock signal in which a base clock signal having a base frequency is generated to provide two clock signals of slightly different frequencies with defined time or phase delay. Here, the base frequency is divided by a first integer to produce a first auxiliary signal, the frequency of the first auxiliary signal is multiplied by a factor to obtain the first clock signal, the base frequency is further divided by a second integer to produce a second auxiliary signal, and the frequency of the second auxiliary signal is multiplied by the factor to obtain the second clock signal.

Systems, apparatus, methods and computer program products are provided for causing a dataframe to be emitted at an air interface of an antenna. A memory stores a transmission to antenna delay value (TAD). An offset calculator calculates an offset value based on an epoch of a global timebase generator and the transmission to antenna delay value (TAD). An interface controller in communication with the offset calculator communicates a segment synchronization signal and a field synchronization signal based on the offset value.

The invention discloses a stable image processing system comprising a image sensor, an image processing circuit connected with the image sensor, a time base generation circuit connected with the image processing circuit, a signal filtering circuit simultaneously connected with the image processing circuit and the time base generation circuit and a bias amplifying circuit connected with the time base generation circuit. The stable image processing system is characterized by further comprising a phase-shift circuit connected with the bias amplifying circuit; the phase-shift circuit comprises a phase-shift chip U2, a triodeVT4, a triodeVT5, a resistor R14, a capacitor C3 and the like; one end of the resistor R14 is connected with a VCC+ pin of the phase-shift chip U2, and the other end of the resistor R14 is connected with an IN1 pin of the phase-shift chip U2; a cathode of the capacitor C3 is connected with the IN1 pin of the phase-shift chip U2 through a resistor R16, and an anode of the capacitor C3 is connected with an IN2 pin of the phase-shift chip U2. Compared with the prior art, the stable image processing system is provided with the phase-shift circuit to ensure processing effect of the processing system as the voltage is unstable, thus image signal distortion after processing never occurs.

An intelligent lighting control system, a control method, and an intelligent lighting system, the intelligent lighting control system comprising: a main controller, a PWM data buffer controller, and a time base generator, wherein: the main controller is adapted to receive user input the dimming instruction, generate the corresponding target pulse width adjustment parameter according to the dimming instruction, send the target pulse width adjustment parameter to the PWM data buffer controller, and send the PWM wave to the PWM data buffer controller Generate instructions; the PWM data buffer controller is adapted to store the target pulse width adjustment parameters, and when receiving the PWM wave generation instructions, control the time base generator to generate and adjust the target pulse width parameters Corresponding PWM wave; the time base generator is adapted to generate a PWM wave corresponding to the target pulse width adjustment parameter, and input the generated PWM wave to the LED driving circuit. The above-mentioned solution can reduce the demand on the computing performance of the MCU when the LED lighting equipment performs dimming.

The invention provides a fixed-time dynamic area tracking control method based on Time Base Generator, which includes the following steps: establishing a fixed-time distributed state observer to estimate the center position of the tracked area, then setting a reference point according to the center position, and finally designing a fixed time The time controller enables the multi-agent to track the upper reference point at any given time and keep it all the time, thus realizing fixed-time dynamic region tracking. The stability time of this method is not affected by the initial state of the system, which enables the multi-agent system to track the specified area at any given time, and the fixed time method based on the Time-Base Generator has a smaller energy input and a more concise system. parameters to improve the applicable scope of the system.