The present invention relates to a frequency-shift-
keying demodulator (1,1') comprising a phase shifter 2 for shifting the phase of an input
signal i(t) by a predetermined degree and for outputting a shifted
signal Id(t), a combining unit (3, 4; 31, 32, 33, 41, 42) for combining the input
signal i(t) and the shifted signal Id(t) output by the phase shifter 2 and for outputting a corresponding signal r(t) and a low-pass filter 5 for filtering the signal r(t) output by the combining unit (3, 4; 31, 32, 33, 41, 42), and for outputting a low-pass filtered signal r LP (t) the bandwidth of said low-pass filter 5 being matched with the bandwidth of a
data signal contained in said input signal i(t). According to the present invention said combining unit (3, 4; 31, 32, 33, 41, 42) comprises at least one
adder (3; 31, 32) for adding the input signal i(t) and the shifted signal Id(t) output by the phase shifter 2 and for outputting an added signal and at least one
square law detector (4; 41, 42) for receiving the added signal output by the
adder (3; 31, 32) and for outputting a squared signal r(t) which is the square of the added signal wherein the combining unit (3, 4;31, 32, 33, 41, 42) outputs the squared signal r(t) to the low-pass filter 5. Furthermore, the present invention relates to a method of frequency-shift-
keying demodulating an input signal i(t).