52 results about "Software simulator" patented technology

In a debugging system for use in realizing simultaneously complete observation of internal operation and reproduction of malfunction actually caused in a target system which includes an integrated circuit, such as a microprocessor, contents of a memory and an internal initial state of the target system are snooped and stored in a snoop unit and a trace memory, respectively, both of which are included in a probe unit attached to the target system. The internal operation and the reproduction are simulated by a software simulator model by the use of the contents and the internal initial state which are stored in the trace memory and which are sent from the probe unit.

An operation training simulation system for a computer numerical control (CNC) machine includes a physical control device for inputting control and operation commands, a software simulator connected with the physical control device, a transmission apparatus connecting the physical control device with the software simulator and a simulation display electrically connected to the software simulator. The software simulator generates machining and operation simulations based on the inputted control and operation conditions through the physical control device, and the simulation display visualizes the machining and operation simulations generated by the software simulator. Therefore, using the operation training simulation system for CNC machine not only eliminates the consumptive materials cost but also solve the personal injury problem. Consequently, the learning efficiency of the trainees and the familiarization to machine are raised in this way.

A power estimation system uses a hardware accelerated simulator to advance simulation to a point of interest for power estimation. The hardware accelerated simulator generates a checkpoint file, which is then used by a software simulator to initiate simulation of the processor design model for power estimation. An on-the-fly power estimator provides power calculations in memory. Thus, the power estimation system described herein isolates instruction sequences to determine portions of software code that may consume excess power or generate noise and to provide a more accurate power estimate on the fly.

A method and apparatus for development and concurrent verification of digital designs including a combination of a microprocessor and discrete logic design blocks. The hardware/software design development and co-verification processing of digital designs is accelerated by placing the microprocessor in an FPGA device and logic circuits in an HDL simulator. The microprocessor and logic circuits are connected via a common bus and synchronization of both environments is achieved by using a simulator clock exclusively when both microprocessor and logic simulator need to communicate with each other. The system and method of the present invention provides a unique arrangement of a processor clocking scheme. An essential part of the invention is a clock switch responsive to the areas of RAM a processor is addressing and accordingly switching a clock signal to the processor from either a hardware clock generator or a software simulator.

According to the present invention, there is provided a simulation apparatus having, a hardware emulator which includes a first CPU core as a simulation target, and a debug control unit; a software simulator which includes a second CPU core as a simulation target, and a clock generation unit which generates a clock and supplies the clock to the first CPU core and the second CPU core; and a debugger which debugs the first CPU core and the second CPU core and in which a clock disable condition is set, wherein upon determining that the clock disable condition set in the debugger is satisfied, the debug control unit outputs a clock disable signal, and upon receiving the clock disable signal, the clock generation unit stops generating the clock.

A monitoring system monitors a system that has multiple devices that perform respective primary tasks. For the purpose of the monitoring, each device has a finite state machine (FSM) with stochastic non-periodic behavior. The monitoring system simulates in software the behavior of the FSM's. A discrepancy between the states assumed by the FSM's after each time step and the states assumed in the simulation in each time step indicates a failure or a breach of the network's integrity. Hacking such as primary system is practically impossible without being detected. Each device comprises computational resources. In order to reduce the computational environment available to a virus, the idle time of the resources is absorbed by dynamically increasing the complexity of the FSM's.

The invention relates to a distributed software reliability evaluating system with time constraint, comprising of reliability evaluator on the main control terminal, simulator on each node machine in the distributed system and distribution software simulator. The reliability evaluator is used for receiving configuration file and doing original configuration, controlling simulation of simulator to the node machine; the simulator is used to received test information sent from the reliability evaluator, and executable program and data file from the simulator of the distributed software; the simulator of the distributed software is generating program in program listing and data file in file program listing and distributing them with random to simulator of node machine.

A computer implemented method, data processing system, and computer usable code are provided the generation of software thermal profiles for applications executed on a set of processors in a simulated environment. Execution of a software program being run on a software simulator is detected and hardware operations for the software program being executed by the set of processors are analyzed to create analyzed information. Then, a thermal index is generated based on the analyzed information.

The content disclosed by the invention relates to a computer program executed on computer equipment, belongs to the special technical field of computer system software, and especially focuses on software debugging systems and debugging methods for detecting computer program errors. The provided post-execution software debugging system framework having performance display contains a called program,an operation system running the called program, a called program source code file, a called program mapping file, display equipment, a tracking record module, a tracking analysis module, an instruction address value database, a software simulator, an event analysis module, a performance analysis module, a coverage analysis module and a debugger. A debugging method is provided based on the software debugging system, and therefore, post-execution debugging for software can be achieved; and the method is helpful for finding reproducible bugs and non-reproducible bugs in computer programs.

The invention provides a data type conversion-based hardware simulator validation data extraction system. The system comprises a SystemVerilog unit and a SystemC unit, wherein the SystemVerilog is used for receiving input data sent from an external hardware simulator, checking the input data, packing the data into a data package and then sending the data package to the SystemC unit; and the SystemC unit is used for 6 data types defined in SystemVerilog into 6 data types defined in SystemVerilog according to a one-to-one corresponding manner, sending the data package to a software simulator according to the simulation precision of the software simulator, extracting the running result of a tested unit running on the hardware simulator with relatively high efficiency, and comparing the running result with a structure preset in the software simulator on a workstation so as to realize the determination of the running result of the tested unit. The method has the advantages of being flexible in data package, high in simulation speed and flexible in software simulator interface.

A kind of stimulation device of operation training for CNC machine tool includes control device for entity, software simulator, transmitting device and stimulating display device; the control device for entity provides operation command; the software simulator is connected with the control device, and generates the stimulation of operation action according to operating action command input by the control device for entity; the transmitting device connects with the control device for entity and the software simulator; the stimulating display device is connected with the software simulator and display the operating action stimulation generated by the software simulator.

Virtual Real Time (VRT) provides high fidelity timing for software simulator environment running in a workstation. VRT is scalable and controllable. VRT provides flight and simulation software synchronization mechanism. This feature guarantees that the causality effect between flight software when interacting with simulated devices is the same as running flight software in a real test-bed environment. VRT provides high-resolution timing, which facilitates monitoring and detection of timing related faults while running the simulation software system on a workstation. VRT is modularized, such that the switchover from virtual clock to real clock is a trivial task. Running the system on a workstation using VRT behaves exactly like a real system, with the added benefits of user controllable features such as start, stop, monitor and time-scale. Performance of systems running with VRT is generally very good, equal to or better than the hardware, as the software runs natively on a faster workstation.

The present invention relates to the field of computer software simulators, and discloses a simulator and a content recording and playing method. The simulator comprises a recording unit, a guiding unit, a storage unit, a display unit, a processing unit and a playing unit, wherein the storage unit is used for recording times of click operation of a mouse or a keyboard and relative displacement coordinates of movement of the mouse during a recording process, sending the record to the display unit, and simultaneously recording timestamps corresponding to the times of click operation of the mouse and the keyboard and timestamps corresponding to the relative displacement coordinates of movement of the mouse. According to the simulator and the content recording and playing method based on the simulator, the recorded contents can be automatically readjusted according to window sizes, resolution or position variation without debugging each recording action again by users, and the recorded contents can help the users to complete a portion of repeated cycle operation.

The invention discloses a method and system for managing an event queue of a software simulator of a microprocessor. The method and the system are used for overcoming the defect in the prior art that the efficiency of the event queue of the software simulator of the microprocessor is low. The method comprises the steps: the event queue is stored in a circular array; the circular array contains a plurality of table entries, and each table entry corresponds to one clock cycle of the software simulator; all the table entries in the circular array are enabled to be in one-to-one correspondence to preset linear chain tables, and a head pointer and a tail pointer of each table entry respectively point to a head element and a tail element of a corresponding linear chain table; each linear chain table stores events, which should be triggered in the clock cycle represented by corresponding table entry; a global cycle pointer is enabled to point to the table entry corresponding to the current clock cycle; after the simulation of one clock cycle ends, the global cycle pointer goes forwards by one table entry. The method and the system disclosed by the invention have very high efficiency in the aspects of event insertion, event query and event removal.

The invention relates to a method for realizing a multi-mode big data software simulator. The method comprises the following steps: 1, generating an XML file dictionary needing to call and characterize equipment parameter information according to a keyword search mode by designing an XML file for characterizing the mode information by utilizing menu content; 2, realizing automatic structured generation of interface elements by taking flow layout panel (Flow Layout Panel) control as a container by virtue of design of multiple user-defined controls; 3, realizing automatic framing when interface parameter data changes by virtue of a mode of interpreting the interface control and XML file in parallel. According to the method disclosed by the invention, multi-mode logical relation is simply realized through associated design, big data can be called by respectively compiling XML files and depending on multi-mode logical relation, interface generation is conveniently realized by virtue of an automatic software interface generation technology, the working efficiency is greatly improved, and the labor intensity is reduced.