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44 results about "Silicon on sapphire" patented technology

Silicon on sapphire (SOS) is a hetero-epitaxial process for metal-oxide-semiconductor (MOS) integrated circuit (IC) manufacturing that consists of a thin layer (typically thinner than 0.6 µm) of silicon grown on a sapphire (Al₂O₃) wafer. SOS is part of the silicon-on-insulator (SOI) family of CMOS (complementary MOS) technologies. Typically, high-purity artificially grown sapphire crystals are used. The silicon is usually deposited by the decomposition of silane gas (SiH₄) on heated sapphire substrates. The advantage of sapphire is that it is an excellent electrical insulator, preventing stray currents caused by radiation from spreading to nearby circuit elements. SOS faced early challenges in commercial manufacturing because of difficulties in fabricating the very small transistors used in modern high-density applications. This is because the SOS process results in the formation of dislocations, twinning and stacking faults from crystal lattice disparities between the sapphire and silicon. Additionally, there is some aluminum, a p-type dopant, contamination from the substrate in the silicon closest to the interface.

Integrated photodetector for VCSEL feedback control

An integrated photodetector means for controlling the output of a light source, where the control means is a photodetector formed on a silicon-on-insulator substrate. The integrated photodetector senses the optical power from the light source and provides an electrical feedback signal which can be used to adjust the DC bias levels of the light source control driver circuit. The approach readily lends itself to large arrays of light sources bonded to silicon-on-sapphire driver circuits and is especially suitable for controlling light sources such as VCSELs in arrays such as are found in communications systems.
Owner:PEREGRINE SEMICONDUCTOR

Coupling waste heat into batteries

A system for maintaining battery temperatures for energy storage systems using heat created by power electronic device needed to interface the batteries to external power sources or loads is described. Waste heat is a product of internal resistance found in all electronic devices passing current. High-temperature electronics comprised of, silicon-on-insulator, silicon-on-sapphire, silicon-carbide, gallium-nitride or in conjunction with or combination of other wide bandgap semiconductors can used to monitor, charge or discharge the battery array. A thermal system where heat generated by power electronics is used to assist the thermal management of battery energy storage system increases overall system efficiency.
Owner:NORMANN RANDY ALLEN

Silicon-on-insulator wafer having conductive layer for detection with electrical sensors

A method for fabricating a silicon-on-sapphire wafer for processing by silicon-wafer-processing equipment. A layer is deposited on a backside of a silicon-on-sapphire wafer, the layer having optical and electrical properties of silicon, wherein the silicon-on-sapphire wafer may be sensed by a sensor designed to sense a presence of a silicon wafer.
Owner:IBM CORP

Receiver electronics proximate antenna

A resistivity tool includes receiver electronics near each receiver antenna loop. Placement of the electronics in this position such as at the circuit card between the terminal ends of the receiver antenna loop improves signal to noise ratio by reducing or eliminating interference, noise, and cross-talk of transmissions from the receiver to a remote microprocessor. By using material such as silicon-on-sapphire, electronics can be miniaturized and operate reliably at when exposed to high temperatures, even for long periods.
Owner:HALLIBURTON ENERGY SERVICES INC +1

Approach for an Area-Efficient and Scalable CMOS Performance Based on Advanced Silicon-On-Insulator (SOI), Silicon-On-Sapphire (SOS) and Silicon-On-Nothing (SON) Technologies

The invention provides the guided design approach to optimize the device performance for a best area-efficient layout footprint in a single-leg MOS device that is based on any of the SOI, SOS or SON technologies. The design methodology depends on a new proprietary device architecture that is also being claimed in this patent and that allows the implementations of the design equations of our methodology.
Owner:TARAKJI AHMAD

Radiation-hardened silicon-on-insulator CMOS device, and method of making the same

A method for eliminating the radiation-induced off-state current in the P-channel ultrathin silicon-on-sapphire transistor, by providing a retrograde dopant concentration profile that has the effect of moving the Fermi level at the back of the device away from that part of the bandgap where the interface states are located. When the Fermi level does not swing through this area in any region of operation of the device, subthreshold stretchout of the I-V curves does not occur.
Owner:CABLE JAMES S +3

Radiation-hardened silicon-on-insulator CMOS device, and method of making the same

A silicon-on-insulator metal oxide semiconductor device comprising ultrathin silicon-on-sapphire substrate; at least one P-channel MOS transistor formed in the ultrathin silicon layer; and N-type impurity implanted within the ultrathin silicon layer and the sapphire substrate such that peak N-type impurity concentration in the sapphire layer is greater than peak impurity concentration in the ultrathin silicon layer.
Owner:PSEMI CORP
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