169 results about "Pwm modulator" patented technology

A class AD audio amplifier system (10) with DC output detection logic (26) is disclosed. The amplifier system (10) includes multiple audio channels (20), each of which includes a pulse-width-modulator (PWM) (24). The DC detection logic (26) includes a sigma-delta modulator (60) and a digital low-pass filter (62) that monitors the PWM output signals from the PWM modulators (24). The sigma-delta modulator (60) operates at a first clock frequency, while the low-pass filter (62) operates at a much lower clock frequency, so that AC audio components, PWM harmonics, and sigma-delta quantization error is suppressed from the DC detection. The modulated filtered signal is compared against a threshold level (THRSH) to determine whether the amplitude of a DC component at the PWM output is sufficiently high to constitute a fault. If so, a fault detection signal (DC_DET) is issued, and the PWM modulators (24) are disabled to prevent unsafe conditions in the system (10).

A space vector pulse-width modulator (SVPWM) and a method implemented by the modulator. A precalculation module accepts Ua and Ub modulation indexes and in response thereto, outputs modified Ua and Ub information; a sector finder has a U module which receives the modified Ua information and outputs a U sector; and a Z module which receives the U sector and the modified Ub information and outputs a Z sector. The U sector and the Z sector are 2-phase control signals for implementing 2-phase modulation. For 3-phase modulation, the SVPWM and method further possess an active vectors calculation module and an assign vectors module which receive the modified Ua and Ub information and the U sector, and which calculate active vectors for 3-phase modulation; a zero vector selector which receives the Z sector and calculates zero vectors for 3-phase modulation; and a PWM counter block which receives the active vectors and zero vectors and outputs 3-phase control signals for implementing 3-phase modulation. The SVPWM and method may have a symmetrical PWM mode, an asymmetrical PWM mode, or both. Advantageously there may also be a rescale and overmodulation module which receives duration information corresponding to the vectors and in response thereto, detects the occurrence of overmodulation. Overmodulation may be detected in response to a negative zero vector time. The module may respond to overmodulation by clamping the zero vector time to zero and rescaling the active vector times to fit within the PWM cycle. The rescaling may restrict a voltage vector to stay within hexagonal boundaries on the space vector plane, while preserving voltage phase.

A class AD audio amplifier system (10) with improved recovery from clipping events is disclosed. The amplifier system (10) includes multiple audio channels (20), each of which can be constructed to include a pulse-width-modulator (PWM) (24). The PWM modulator (24) includes a pair of comparators (39A, 39B; 52+, 52−) that generate complementary PWM output signals based upon the comparison between a filtered difference signal and a reference waveform. Clip detection logic (26) is provided to detect clipping at the output of the channel (20), preferably by detecting successive edges of the reference waveform without an intervening edge of a PWM output signal. In response to detecting clipping, a first integrator (30; 45) is reset to remove residuals and to eliminate the first integrator (30; 45) from the loop filter of the modulator (24). A saturation level circuit (35) applies a clamping voltage, preferably in both clipping and non-clipping situations, to a second integrator (36; 47). As a result, the loop filter is prevented from entering extreme conditions during clipping, which greatly reduces the clipping recovery time.

A circuit for transitioning between a discontinuous and a fixed frequency continuous conduction mode (DCM) and (CCM) of a power converter having a driver receiving PWM signals and controlling a switching stage comprises a control switch and a sync switch connected at a common switching node for driving a load. The circuit including a PWM modulator for providing PWM signals; and a mode selector for receiving a duty cycle value, a preset switching period, and a duty cycle at a critical conduction point having a switching frequency equal to the preset switching period and providing an on-time of the control switch and a switching period to the PWM modulator, wherein if the duty cycle value is greater than the duty cycle at a critical conduction point, the PWM modulator will drive will provide the PWM signals to operate the switching stage in the CCM with constant-frequency duty cycle control, and if the duty cycle value is less than duty cycle at a critical conduction point, the PWM modulator will drive will provide the PWM signals to operate the switching stage in the DCM by turning off the sync switch when a load current becomes negative.

A class AD audio amplifier system (10) with reduced noise capability in muting and unmuting events is disclosed. The amplifier system (10) includes multiple audio channels (20), each of which can be constructed to include a pulse-width-modulator (PWM) (24). The PWM modulator (24) includes a pair of comparators (39A, 39B; 52+, 52−) that generate complementary PWM output signals based upon the comparison between a filtered difference signal and a reference waveform. When the system is muted, a common mode voltage (CM_RAMP) is applied to the inputs of the comparators (39A, 39B; 52+ 52−) to suppress the duty cycle at the amplifier output, preferably to a zero duty cycle. In the transition from a muted state to an unmuted state, the common mode voltage (CM_RAMP) is ramped from the suppressing voltage to zero common mode voltage, permitting the duty cycle of the complementary PWM signals to gradually increase, thus reducing clicks and pops. The converse operation is performed in the transition from unmuted to muted. Pulse-width-modulation control logic (26) is also included to ensure that that the PWM “on” and “off” pulses are of at least a minimum duration, and also to generate compensating pulses on the complementary PWM line at low duty cycles.

A single monolithic integrated circuit (10) containing a solar cell (or cells) with a DC-DC converter includes: a substrate (120, 220); the solar cell (101) or a solar cell array (100, 100′) on the substrate for generating an output voltage; and the DC-DC converter (102) integrated on the substrate for receiving the output voltage to generate a converted voltage, which may be higher or lower than the solar generated voltage. The substrate may be a silicon <111>, silicon carbide, or sapphire substrate. A GaN RF power amplifier and a CMOS controller including PWM modulator may also be monolithically integrated with an InGaN solar cell array and a GaN DC-DC converter. GaN switches (113, 115, 117, 119) may be used to couple InGaN solar cells (101) in series or parallel within the solar cell array (100, 100′) to yield improved or optimal voltage and current levels as required by the load.

An audio amplifier receiving a digital input audio signal and generating an output audio signal for driving a speaker includes a digital input class D amplifier configured to receive the digital input audio signal and to generate the output audio signal. The digital input class D amplifier includes a first modulator configured to receive the digital input audio signal and to generate a quasi-digital signal in n-bit, and a class D modulator configured to receive the n-bit quasi-digital signal and to generate the output audio signal, the class D modulator implementing an analog feedback loop. In some embodiments, the class D modulator is implemented using a PWM modulator. In other embodiments, the PWM modulator incorporates enhanced features to improve the output noise characteristics.

A pulse width modulation (PWM) modulator for a multiphase power converter and related adaptive firing order (AFO) method includes a multiphase leading edge generator having pulse generating circuitry associated with each of the regulator phases, wherein the pulse generating circuitry generates phase pulses associated with each of the phases. An adaptive firing order (AFO) controller having circuitry including a mixer receives and sums the phase pulses into a summing signal and uses the summing signal to generate a series of turn-on pulses therefrom. A multiphase PWM generator has inputs coupled to an output of the AFO controller coupled to receive the series of turn-on pulses, the multiphase PWM generator having circuitry for generating said PWM signals therefrom. An adaptive firing order (AFO) controlled multi-phase power converter includes a plurality of parallel connected regulator phases controlled by respective pulse width modulation (PWM) signals provided by the PWM modulator.

The present invention relates to pulse width modulation (PWM) modulators, especially but not exclusively for digital audio applications; and to quantizers and power switching for the same. The present invention provides a pulse width modulation (PWM) modulator or converter having a guard band quantizer arranged to block low level signal inputs to the modulator in order to prevent narrow width output pulses. This arrangement is particularly advantageous when applied to tri-level PWM modulators, but can also be applied to other level PWM modulators such as bi-level for example. Quantization noise can be reduced by implementing the quantizer in a noise shaper circuit (or possibly a SDM) having loop feedback.

A space vector pulse-width modulator (SVPWM) and a method implemented by the modulator. A precalculation module accepts Ua and Ub modulation indexes and in response thereto, outputs modified Ua and Ub information; a sector finder has a U module which receives the modified Ua information and outputs a U sector; and a Z module which receives the U sector and the modified Ub information and outputs a Z sector. The U sector and the Z sector are 2-phase control signals for implementing 2-phase modulation. For 3-phase modulation, the SVPWM and method further possess an active vectors calculation module and an assign vectors module which receive the modified Ua and Ub information and the U sector, and which calculate active vectors for 3-phase modulation; a zero vector selector which receives the Z sector and calculates zero vectors for 3-phase modulation; and a PWM counter block which receives the active vectors and zero vectors and outputs 3-phase control signals for implementing 3-phase modulation. The SVPWM and method may have a symmetrical PWM mode, an asymmetrical PWM mode, or both. Advantageously there may also be a rescale and overmodulation module which receives duration information corresponding to the vectors and in response thereto, detects the occurrence of overmodulation. Overmodulation may be detected in response to a negative zero vector time. The module may respond to overmodulation by clamping the zero vector time to zero and rescaling the active vector times to fit within the PWM cycle. The rescaling may restrict a voltage vector to stay within hexagonal boundaries on the space vector plane, while preserving voltage phase.

The invention relates to a method and a device for controlling voltage zero crossing point current distortion of a totem-pole PFC. Input and output voltage information and inductance current information are sampled through a sampling module; error signals are compensated and adjusted through a voltage outer loop adjusting unit and a current inner loop adjusting unit; and finally the processed error signals are sent to a PWM modulator to generate a gating signal. The zero crossing point state of the input voltage of each half of the power frequency period is detected to be inserted into dead zone control and bipolar control; soft start of a main switch tube of a high-frequency bridge arm in the dead zone control stage is completed, and the inductance current is constrained without generating a pulse peak; and in the bipolar control stage, the current constraint condition also can be established under the condition that the input voltage is relatively low, so that the input current can be more effectively corrected to enable the input current to follow the input voltage. The device can be stably operated in a CCM control mode, and the problem of zero crossing point pulse is solved, so that the overall power factor value is improved, and the total harmonic distortion amount of the whole system is reduced.

A pulse width modulation (PWM) modulator includes an integrator generating an integrated signal based on an input signal and an output signal, a low pass filter (LPF) receiving the integrated signal and performing low pass filtering, a comparator receiving an output signal of the LPF and a predetermined reference signal, comparing the received signals, and outputting a PWM signal, a dead time setup block outputting a first signal and a second signal having a predetermined phase difference therebetween based on the PWM signal, and a power stage buffering the first and second signals and generating the output signal based on a result of buffering. In the PWM modulator and a class-D amplifier having the PWM modulator, EMI can be reduced.

The invention provides a rapid dynamic compensation control apparatus and control method of a voltage control type DC / DC converter. The rapid dynamic compensation control apparatus comprises a voltage controller (Gv), a voltage compensation module (VCM), a current limiting module (CLM) and a PWM modulator. Due to the restriction of the switching frequency of a power switch device, the bandwidth of the control loop of a medium and large-power converter is quite low, under general voltage closed loop control, and in case of a load abrupt change, quite large fluctuations are caused to output voltages. Direct correction is carried out on a digit control amount which adjusts a duty ratio in a control system according to the inherent open loop characteristic of a tested converter itself, such that the purpose of rapid compensation is achieved.

The present invention provides a VCM driver realizing low power consumption and high accuracy and a PWM amplifier compensating a dead time distortion. A phase compensator, a ΔS modulator receiving an output signal of the phase compensator and converting the output signal to a control code of predetermined bits, a PWM modulator receiving the control code to produce a PWM signal, and an output circuit receiving the PWM signal to drive a voice coil constitute a forward path. A sense amplifier sensing a current of the voice coil, an ADC receiving an output signal of the sense amplifier, a low-pass filter receiving an output signal of the ADC, and a decimation filter receiving an output signal of the low-pass filter constitute a feedback path. An output signal of the decimation filter is fed back to the input side of the phase compensator to form a major feedback loop having a first-order characteristic loop gain. An output signal of the decimation filter is fed back to the output side of the phase compensator to form a minor feedback loop having a loop gain which is flat until a target band frequency when viewed from the output side of the phase compensator.