31 results about "Word clock" patented technology

The present invention provides a data transfer system including a data transmitter and a data receiver. The data transmitter converts a plurality of bits of transmission parallel data into serial data and generates a multi-level logic signal representing a plurality of bits of information in one symbol, the information being obtained by combining the serial data with a word clock as one-bit information. The word clock indicates a word delimiter in the serial data. The data receiver receives the transmitted multi-level logic signal, extracts the serial data and the word clock from the signal, and reproduces the parallel data based on the extracted word clock. In the data transfer system, a multi-bit digital signal can be transmitted as one signal including a word clock. Thus, components and mounting space to be allocated to transfer can be reduced.

A waveform data processing apparatus has a bus that transfers data signals representative of waveform data. A plurality of transmitting nodes transmit the data signals to the bus. A plurality of receiving nodes receive the data signals from the bus. A clock generator generates a word clock signal at each sampling period. A controller is responsive to the word clock signal for conducting a session of transferring the data signals within a sampling period, such that the transmitting nodes sequentially transmit the data signals in an order predetermined by the controller so as to avoid collision of the data signals within the sampling period, and each of the receiving nodes selectively admits a necessary one of the data signals outputted from the transmitting nodes and processes the admitted data signal within the sampling period.

The invention relates to a method for realizing modulation coding of a digital storage product. In the digital storage product, modulation coding is required to be performed on user information to meet channel transmission limit and digital clock restoring performance, and a digital clock can be well restored by generally adopting a run length limit coding form. The method designs a method for realizing modulation coding on the basis of meeting a clock restoring requirement, i.e., a run length rate (RLR) modulation coding method. The method comprises the following steps of: (1) performing RLR modulating coding on binary information which is subjected to error correction coding; and (2) controlling the recording mark length of a physical recording medium and the formation of a microstructure by using data information which is subjected to RLR rate modulation coding.

A digital clock generator for a digital clock domain interfaced to another clock domain through a FIFO, includes division selector circuitry to provide an input randomizing sequence of clock division factors, selected from a defined set of clock division factors corresponding to a target average clock division, and division arbitration circuitry to generate a drift-corrected randomizing sequence of clock division factors, based at least in part on the input randomizing sequence of clock division factors, and an accumulated drift correction signal. A clock drift control loop generates the accumulated drift correction signal, based at least in part on an accumulated clock drift relative to the target average clock division. Clock generation can be based on randomized division with the drift-corrected randomizing sequence of clock division factors. The drift-corrected randomizing sequence of clock division factors can be generated so that clock drift is bounded based on a FIFO depth.

In an audio processing apparatus configured to supply audio data to a processor configured to process audio data, a plurality of receivers, each configured to receive audio data and a work clock carried with the audio data and to supply the audio data to the processor; a plurality of PLL circuits corresponding to the plurality of receivers, each PLL circuit being configured to generate a clock signal based on a word clock received by the corresponding receiver; and a selector configured to select a clock signal from among a plurality of clock signals generated by the plurality of PLL circuits, and to supply the selected clock signal to the processor, the processor outputting the processed audio data at timing synchronized with the selected clock signal are provided.

A sampling frequency conversion device comprises an internal circuit for executing in synchronization with an internal clock a signal processing of input data fetched in accordance with an input word clock, and for outputting the input data having undergone the signal processing as output data, a clock generation circuit for generating from the internal clock an output word clock and a counter clock having a frequency which is equal to that of the output word clock multiplied by n (n: integer equal to two or more), a counter for counting the counter clock, and a register for holding a counter value of the counter in synchronization with the input word clock, and for outputting the held counter value to the internal circuit.

The invention provides a fractional frequency all-digital phase-locked loop and a control method of the fractional frequency all-digital phase-locked loop. The method includes: S1, the fractional frequency controller generates a delay control word, a frequency division ratio control word, an integer frequency control word and a fractional frequency control word according to an external fractional frequency control word; S2, the clock generation and control circuit is based on the reference clock, The frequency control word generates the clock signal ckr; S3, the digital time converter generates the low frequency clock signal according to the ckr and the delay control word; S4, the feedback signal generating circuit outputs the high frequency clock signal ckv generated according to the frequency division ratio control word and the numerical control oscillator The feedback signal fb; S5, the phase detector generates the phase error digital signal phe of ckr and fb; S6, the auxiliary frequency locked loop outputs the control signal ftl according to the integer frequency control word, the fractional frequency control word and the low frequency clock signal, and the numerical control oscillator according to The addition of ftl and phe and the update of ckv.

The present invention proposes a spread-spectrum modulation method for a filter-free digital class D audio power amplifier, which utilizes the main clock signal of the power amplifier clk and UPWM generator input synchronous word clock signal clk_s 1 Synthesize another clock signal according to certain rules clk_s 2. Then build a pseudo-random number generator to generate a series of pseudo-random numbers, by judging the parity of the pseudo-random numbers, using the clock signal clk_s 1 and the clock signal clk_s 2 Synthesize a clock signal with variable frequency clk_c , and finally using the master clock signal clk , clock signal clk_c And the amplitude of the input signal of the UPWM generator is processed by the threshold calculator, counter and comparator to output the PRF variable left-increasing double-edge UPWM signal; at the same time, the corresponding filter-free pulse width modulator is designed based on the above-mentioned spread spectrum modulation method. The invention can obviously reduce the amplitude of the high-frequency component of the UPWM signal output by the power amplifier, thereby reducing EMI, and is simple to implement and requires less hardware resources.