3D stacked memory, clock skew elimination method and clock skew elimination circuit

Abstract

The invention discloses a clock skew elimination method of a 3D stacked memory, a clock skew elimination circuit of the 3D stacked memory and the 3D stacked memory. The clock skew elimination method comprises the following steps: generating a preset digital clock phase according to an original signal phase of a write data gating pin and original signal phases of all data pins, so as to enable thepreset digital clock phase to lag behind the original signal phase of the data gating pin and the original signal phase of each data pin; comparing the original signal phase of each data pin with a preset digital clock phase, and delaying the original signal phase of each data pin to ensure that the signal phase of each data pin is consistent with the preset digital clock phase. According to the embodiment, delay control is carried out on each data pin according to the preset digital clock phase, so that pin deflection is eliminated, and the data transmission reliability of the 3D stacked memory is improved.

Description

technical field [0001] The present application belongs to the technical field of electronic circuits, and in particular relates to a clock skew elimination method for a 3D stacked memory, a clock skew elimination circuit for a 3D stacked memory, and a 3D stacked memory. Background technique [0002] With the rapid development of electronic technology, large-scale integrated circuits have gradually been widely used in the daily industrial production process. Since electronic equipment will generate a large amount of data input and output during work, in order to ensure the stability and safety of electronic equipment Therefore, it is necessary to store and retain the data transmitted by the electronic equipment in real time, so as to control the electronic equipment in real time according to the stored data; therefore, the storage security and storage capacity of the data will play an important role in the circuit control process of the electronic equipment. Extremely importa...

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Problems solved by technology

[0004] In view of this, the embodiment of the present application provides a clock skew elimination method for a 3D stacked memory, a clock skew elimination circuit for a 3D stacked memory, and a 3D stacked memory, aiming to solve traditional technical solutions for data transmission delay elimination The process will generate a large storage standby power consumption problem

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