Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

3D stack memory, clock skew elimination method and clock skew elimination circuit

A technology of clock skew and memory, which is applied in the field of clock skew elimination circuit and 3D stack memory, can solve the problem of large storage standby power consumption, etc., to reduce standby loss, high accuracy and reliability, and eliminate pin skew effect of error

Active Publication Date: 2022-03-29
SHENZHEN STATE MICROELECTRONICS CO LTD
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In view of this, the embodiment of the present application provides a clock skew elimination method for a 3D stacked memory, a clock skew elimination circuit for a 3D stacked memory, and a 3D stacked memory, aiming to solve traditional technical solutions for data transmission delay elimination The process will generate a large storage standby power consumption problem

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • 3D stack memory, clock skew elimination method and clock skew elimination circuit
  • 3D stack memory, clock skew elimination method and clock skew elimination circuit
  • 3D stack memory, clock skew elimination method and clock skew elimination circuit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0032] In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

[0033] In recent years, the accumulation of big data, the innovation of theoretical algorithms, the improvement of computing power and the evolution of network facilities have made the artificial intelligence industry, which has been accumulated for more than half a century, usher in revolutionary progress again, and the research and application of artificial intelligence have entered the A new stage of development; with the active promotion of the government and the industry, artificial intelligence technology has advanced by leaps and bounds in large-scale industrial appl...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A clock skew elimination method for 3D stacked memory, a clock skew elimination circuit for 3D stacked memory, and a 3D stacked memory. The clock skew elimination method includes: according to the original signal phase of the write data strobe pin and the phases of all data pins The raw signal phase generates the preset digital clock phase such that the preset digital clock phase lags the raw signal phase of the data strobe pin and the raw signal phase of each data pin; compares the raw signal phase of the data pin with the preset The digital clock phases are compared, and the original signal phase of each data pin is delayed to ensure that the signal phase of each data pin is consistent with the preset digital clock phase; Delay control is performed on the data pins to eliminate pin skew and improve data transmission reliability of the 3D stacked memory.

Description

technical field [0001] The present application belongs to the technical field of electronic circuits, and in particular relates to a clock skew elimination method for a 3D stacked memory, a clock skew elimination circuit for a 3D stacked memory, and a 3D stacked memory. Background technique [0002] With the rapid development of electronic technology, large-scale integrated circuits have gradually been widely used in the daily industrial production process. Since electronic equipment will generate a large amount of data input and output during work, in order to ensure the stability and safety of electronic equipment Therefore, it is necessary to store and retain the data transmitted by the electronic equipment in real time, so as to control the electronic equipment in real time according to the stored data; therefore, the storage security and storage capacity of the data will play an important role in the circuit control process of the electronic equipment. Extremely importa...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G11C7/22
CPCG11C7/222
Inventor 邓玉良朱晓锐殷中云方晓伟杨彬庄伟坚苏通李昂阳
Owner SHENZHEN STATE MICROELECTRONICS CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products