A
clock generator including a
frequency multiplier, a phase lock circuit and a
frequency divider. The
frequency multiplier generates a frequency multiplied
clock by multiplying the frequency of an input
clock. The phase lock circuit detects a
phase difference between the input clock and a frequency divided clock, and generates, by delaying the frequency multiplied clock by an amount corresponding to the
phase difference, a phase-locked clock with its phase locked with the input clock. The
frequency divider detects in every fixed cycle a particular pulse of the phase-locked clock, and generates the frequency divided clock by dividing the phase-locked clock with reference to the particular pulse of the phase-locked clock. In particular, the
frequency divider detects the particular pulse immediately previous to a falling edge of the input clock. This can reduce the
phase difference between the input clock and the phase-locked clock, and hence to solve a problem of a conventional
clock generator in that a
delay time of a
digital delay line in a phase lock circuit must be lengthened with a reduction in the multiplication number of the frequency multiplied clock, which requires a greater number of
delay elements because of a large occupying area of the
delay elements and a decoder, thereby increasing the circuit scale and cost of a
chip to reduce the multiplication number of the frequency multiplied clock.