131 results about "Nanowire transistors" patented technology

The present invention relates to vertical nanowire transistors with a wrap-gated geometry. The threshold voltage of the vertical nanowire transistors is controlled by the diameter of the nanowire, the doping of the nanowire, the introduction of segments of heterostructures in the nanowire, the doping in shell-structures surrounding the nanowire, tailoring the work function of the gate stack, by strain engineering, by control of the dielectrica or the choice of nanowire material. Transistors with varying threshold voltages are provided on the same substrate, which enables the design of advanced circuits utilizing the shifts in the threshold voltages, similar to the directly coupled field logic.

An insulated gate silicon nanowire transistor amplifier structure is provided and includes a substrate formed of dielectric material. A patterned silicon material may be disposed on the substrate and includes at least first, second and third electrodes uniformly spaced on the substrate by first and second trenches. A first nanowire formed in the first trench operates to electrically couple the first and second electrodes. A second nanowire formed in the second trench operates to electrically couple the second and third electrodes. First drain and first source contacts may be respectively disposed on the first and second electrodes and a first gate contact may be disposed to be capacitively coupled to the first nanowire. Similarly, second drain and second source contacts may be respectively disposed on the second and third electrodes and a second gate contact may be disposed to be capacitively coupled to the second nanowire.

A method of forming a GAA MOSFET includes providing a substrate having source, drain and channel regions, the substrate doped with one of a p-type and an n-type dopant. Disposing an etch stop-electric well (ESEW) layer over the substrate, the ESEW layer doped with the other of the p-type and the n-type dopant. Disposing a sacrificial layer over the ESEW layer, the sacrificial layer doped with the same type dopant as the substrate. Disposing a channel layer over the sacrificial layer. Patterning a fin out of the ESEW layer, sacrificial layer and channel layer in the channel region. Selectively etching away only the sacrificial layer of the fin to form a nanowire from the channel layer of the fin while the ESEW layer of the fin functions as an etch stop barrier to prevent etching of trenches in the substrate.

The present invention relates to a structure and manufacturing process of a nano device transistor for a biosensor. The structure, the manufacturing process and the related circuit for a carbon nano tube or nano wire transistor biosensor device are provided. The refurbished nano device is used for absorbing various anti-bodies so as to detect the specific antigens or absorbing various biotins. Therefore, the object of the present invention to detect the specific species for bio measurement can be achieved.

A nanowire wrap-gate transistor is realised in a semiconductor material with a band gap narrower than Si. The strain relaxation in the nanowires allows the transistor to be placed on a large variety of substrates and heterostructures to be incorporated in the device. Various types of heterostructures should be introduced in the transistor to reduce the output conductance via reduced impact ionization rate, increase the current on / off ratio, reduction of the sub-threshold slope, reduction of transistor contact resistance and improved thermal stability. The parasitic capacitances should be minimized by the use of semi-insulating substrates and the use of cross-bar geometry between the source and drain access regions. The transistor may find applications in digital high frequency and low power circuits as well as in analogue high frequency circuits.

The invention discloses a junctionless silicon nanowire transistor based on a bulk-silicon material and a method for manufacturing the junctionless silicon nanowire transistor. The junctionless silicon nanowire transistor comprises a bulk-silicon substrate, a polycrystalline grid, a drain electrode, a source electrode and a grid electrode, a P-type doped layer or an N-type doped layer is manufactured on the bulk-silicon substrate, an N-type doped layer or a P-type doped layer with a doping type opposite to the first P-type doped layer or first the N-type doped layer is manufactured on the first P-type doped layer or the first N-type doped layer, and a PN junction is formed by the different types of doped layers and realizes an electric isolation effect; a source region, a drain region and a silicon nanowire are manufactured on the second N-type doped layer or the second P-type doped layer, and the source region and the drain region are connected with each other by the silicon nanowire to form conducting channels; an insulating dielectric layer is manufactured on the surface of the integral silicon nanowire, the surface of the source region and the surface of the drain region; the polycrystalline grid is manufactured between the source region and the drain region and completely wraps the silicon nanowire; the drain electrode is manufactured on the drain region of silicon; the source electrode is manufactured on the source region of the silicon; and the grid electrode is manufactured on the polycrystalline grid. The junctionless silicon nanowire transistor and the method have the advantage that the junctionless silicon nanowire transistor can be manufactured on the bulk-silicon substrate.

A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a gate conductor includes an interfacial layer and a source conductor, and is coaxially wrapped completely around the source region, extending along at least a portion of the source region. A Schottky barrier between the source conductor and the source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.

The invention provides a vertically stacked ring gate nanowire transistor and a preparation method thereof. First, a substrate with channel layers and sacrificial layers on the surface is provided, the channel layers and the sacrificial layers are alternately stacked along a direction away from the substrate, and a mask layer is formed on the outermost sacrificial layer. Then, etching is carried out inwards by starting from the exposed surface of each sacrificial layer so that the two ends with exposed surfaces of the sacrificial layers are recessed inwards relative to the channel layers to form recesses. The recesses are filled with a dielectric material, and thus, the sacrificial layers have substantially the same length. The sacrificial layers are removed to form second grooves, and gate oxide layers and gates are formed in the second grooves. Thus, the finally formed vertically stacked ring gate nanowire transistor has the same gate length. The influence of gate length difference on the performance parameters of devices is effectively avoided. The application competitiveness of the vertically stacked ring gate nanowire transistor is improved.

The invention provides a nanowire transistor and a forming method thereof, wherein the forming method comprises the following steps of: providing a substrate; Forming a composite structure on the substrate, the composite structure comprising one or more laminated composite layers, the composite layers comprising a sacrificial layer on the substrate and a channel layer on the sacrificial layer, thechannel layer and the sacrificial layer being different in material; Etching a sacrificial layer of the side wall of the composite structure to form a depression on the surface of the side wall of the composite structure; Forming an isolation layer on the surface of the sacrificial layer exposed by the recess; Forming a source-drain doping layer on a substrate on both sides of the composite structure after forming the isolation layer, wherein the isolation layer is provided between the source-drain doping layer and the sacrificial layer; Removing the remaining sacrificial layer after the source-drain doping layer is formed; Forming a gate structure surrounding the channel layer. The resulting transistor reduces parasitic capacitance and improves transistor performance.

The present invention is directed to a display using nanowire transistors. In particular, a liquid crystal display using nanowire pixel transistors, nanowire row transistors, nanowire column transistors and nanowire edge electronics is described. A nanowire pixel transistor is used to control the voltage applied across a pixel containing liquid crystals. A pair of nanowire row transistors is used to turn nanowire pixel transistors that are located along a row trace connected to the pair of nanowire row transistors on and off. Nanowire column transistors are used to apply a voltage across nanowire pixel transistors that are located along a column trace connected to a nanowire column transistor. Displays including organic light emitting diodes (OLED) displays, nanotube field effect displays, plasma displays, micromirror displays, micoelectromechanical (MEMs) displays, electrochromic displays and electrophoretic displays using nanowire transistors are also provided.

An insulated gate silicon nanowire transistor amplifier structure is provided and includes a substrate formed of dielectric material. A patterned silicon material may be disposed on the substrate and includes at least first, second and third electrodes uniformly spaced on the substrate by first and second trenches. A first nanowire formed in the first trench operates to electrically couple the first and second electrodes. A second nanowire formed in the second trench operates to electrically couple the second and third electrodes. First drain and first source contacts may be respectively disposed on the first and second electrodes and a first gate contact may be disposed to be capacitively coupled to the first nanowire. Similarly, second drain and second source contacts may be respectively disposed on the second and third electrodes and a second gate contact may be disposed to be capacitively coupled to the second nanowire.

The invention discloses a fabrication method for a surrounding gate silicon nanowire transistor with air as spacers. The method comprises: performing isolation, and depositing a material A which has a higher etch selectivity ratio with respect to Si; performing photolithography to define a Fin hard mask; etching the material A to form the Fin hard mask; performing source and drain implantation; performing photolithography to define a channel region and large source / drain regions; forming the Si Fin and the large source / drains; removing the hard mask of the material A; forming a nanowire; etching the SiO2 to form a floating nanowire; forming a gate oxide layer; depositing a polysilicon; performing polysilicon injection; performing annealing to activate dopants; etching the polysilicon; depositing SiN; performing photolithography to define a gate pattern; etching the SiN and the polysilicon to form the gate pattern; separating the gate and the source / drain with a space in between filled with air; depositing SiO2 to form air sidewalls; performing annealing to densify the SiO2 layer; using subsequent processes to complete the device fabrication. The invention is compatible with the CMOS process flow. The introduction of the air sidewalls can effectively reduce the parasitic capacitance of the device, and improve the transient response of the device, so that the method is applicable for a logic circuit with high performance.