The
multiprocessing apparatus of the present invention is a
multiprocessing apparatus including a plurality of processors, a shared
bus, and a shared
bus controller, wherein each of the processors includes a
central processing unit (CPU) and a local cache, each of the local caches includes a cache memory, and a cache
control unit that controls the cache memory, each of the cache control units includes a
data coherence management unit that manages
data coherence between the local caches by controlling data transfer carried out, via the shared
bus, between the local caches, wherein at least one of the cache control units (a) monitors a local
cache access signal, outputted from another one of the processors, for notifying an occurrence of a
cache miss, and (b) notifies pseudo information to the another one of the processors via the shared bus controller, the pseudo information indicating that data corresponding to the local
cache access signal is stored in the cache memory of the local cache that includes the at least one of the cache control units, even in the case where the data corresponding to the local
cache access signal is not actually stored.