The invention discloses a
chip packaging structure for slowing down
electromagnetic interference and a packaging method thereof. The packaging method comprises the following steps: producing a sinking groove in a
silicon substrate, and embedding a
chip whose front surface is upwards arranged and provided with
welding pads into the sinking groove to save the packaging space; and forming horizontally-arranged or vertically-arranged
inductance distribution wires on the front surface of the
chip and a first surface of the
silicon substrate, forming horizontally-arranged or vertically-arranged
capacitance distribution wires on a first
insulation layer, and extending a first
metal redistribution wire or a second
metal redistribution wire and solder balls to the surface of the
silicon substrate to ensure that the
welding pads of the chip are electrically fanned out of the surface of the silicon substrate and purposes of improving the packaging reliability and achieving simple process and low cost can be achieved. The horizontally-arranged or vertically-arranged
inductance distribution wires form an
inductor, and the horizontally-arranged or vertically-arranged
capacitance distribution wires and
dielectric layers among the
capacitance distribution wires form a
capacitor; and by adopting the
inductor and
capacitor with filter characteristics, the
signal crosstalk among circuits in the chip can be reduced, unnecessary electric signals can be removed by
filtration, the reliability and performance of packaged products can be enhanced, and the cost can also be reduced.