335results about "Resonant circuits using central processing units" patented technology

A tunable receiver is disclosed including a plurality of select filters to perform an initial band selection, a variable-gain low noise amplifier (LNA) whose gain is controlled to prevent its output power level to exceed a predetermined power threshold, a plurality of digitally-tunable tracking filters to pass signals within a selected channel and to reject signals in a corresponding image band, a second LNA to further amplify the received RF signal and to generate differential signal outputs, a down converting stage which converts the received RF signal to an IF signal while rejecting signals in the image band, an IF trap to further reject undesired signals present at the output of the down converting stage, an IF amplifier to amplify the IF signal to compensate for losses, an IF filter to provide channel select and reject undesirable signals, and a variable-gain IF amplifier to amplify the IF signal and maintain its power level within specification.

An integrated front end filter for a tuner provides an array of from several to a multitude of passbands, each for passing at least one but less than all channels designated in a band of frequencies. Each passband is exclusively selectable. The integrated front end filter can include at least one active filter unit with an active reactance element in either of fixed and variable filter configurations and a decoder coupled to said at least one active filter unit and being responsive to a control signal for selecting a one of the passbands. In one example, a multitude of active filter units of fixed filter configuration provide the multitude of passbands. In another example, a plurality of data corresponds to a like plurality of selectable passbands in combination with a filter element of the variable filter configuration. Each data is stored at a predetermined location and reproduced in response to a corresponding control data signal from a tuner controller. Each data characterizes one of the plurality of passbands. The filter element is switchable from one passband to another in response to the control data signal. Lower power dissipation and lesser requirements of an on-following integrated circuitry tuner permit a reduction of “off chip” connections and cost.

A tunable filter has a plurality of variable capacitors and a plurality of inductor elements, each being formed on a common substrate, a filter circuit formed by using at least a portion of the plurality of variable capacitors and a portion of the plurality of inductor elements, a monitor circuit formed by using at least a portion of the plurality of variable capacitors and a portion of the plurality of inductor elements, a detecting circuit which detects a prescribed circuit constant of the monitor circuit, a storage which stores information relating to a reference circuit constant of the monitor circuit, and a capacitance control circuit which controls capacitance of the variable capacitors in the monitor circuit and capacitance of the variable capacitors in the filter circuit, based on a result detected by the detecting circuit and information stored in the storage.

A method and apparatus for compensating an oscillator in a location-enabled wireless device is described. In an example, a mobile device includes a wireless receiver for receiving wireless signals and a GPS receiver for receiving GPS signals. The mobile device also includes an oscillator having an associated temperature model. A frequency error is derived from a wireless signal. The temperature model is adjusted in response to the frequency error and a temperature proximate the oscillator. Frequency error of the oscillator is compensated using the adjusted temperature model. In another example, a frequency error is derived using a second oscillator within the wireless receiver.

In various embodiments, the invention provides a discrete clock generator and / or a timing and frequency reference using an LC-oscillator topology, having a frequency controller to control and provide a stable resonant frequency, which may then be provided to other, second circuitry such as a processor or controller. Frequency stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages. The controlled reactance modules may include fixed or variable capacitances or inductances, and may be binary weighted. Arrays of resistive modules are also provided, to generate one or more control voltages.

In various embodiments, the invention provides a clock generator and / or a timing and frequency reference using an LC-oscillator topology, having a frequency controller to control and provide a stable resonant frequency, which is integrated with other, second circuitry such as a processor or controller. Frequency stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages. The controlled reactance modules may include fixed or variable capacitances or inductances, and may be binary weighted. Arrays of resistive modules are also provided, to generate one or more control voltages.

Systems and methods are described for a GPS receiver capable of functioning in the presence of interference. A method includes detecting an interfering signal including: tuning a band pass filter over a frequency range; and at each of a plurality of incremental frequencies: computing a set of band pass filter coefficients; sending the set of band pass filter coefficients to a digital filter; repeatedly transforming an analog-to-digital converter output having a quantization level in excess of 2 bits into a band pass filter output with the digital filter to obtain a plurality of samples; computing an average of the plurality of samples; and comparing the average to a threshold to detect peaks that exceed a threshold. An apparatus, comprising: an analog radio frequency circuit; an analog-to-digital converter coupled to the analog radio frequency circuit, the analog-to-digital converter providing a quantization level in excess of 2 bits; a digital filter coupled to the analog-to-digital converter; and a digital circuit coupled to the digital filter.

A novel and useful apparatus for and method of spur reduction using computation spreading in a digital phase locked loop (DPLL) architecture. A software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU is adapted to spread the computation of the atomic operations out over and completed within an entire PLL reference clock period. Each computation being performed at a much higher processor clock frequency than the PLL reference clock rate. This functions to significantly reduce the per cycle current transient generated by the computations. Further, the frequency content of the current transients is at the higher processor clock frequency. This results in a significant reduction in spurs within sensitive portions of the output spectrum.

In a cellular phone terminal, the transmitter, receiver, and combiner consist of common hardware that can be used in multiple communication systems. The channel CODEC, modulator, equalizer, and memory for signal processing programs consist of common hardware that performs signal processing supporting multiple communication systems. The CPU and the memory for the communication control program support different communication control systems, thus providing a multi-mode cellular phone terminal supporting different communication systems with simple design and low cost.

An antenna circuit tunable to a determined resonance frequency, includes an antenna coil and adjustable components. The antenna circuit includes a filter having at least one point to tap an electric voltage the amplitude of which forms a pertinent indication for the tuning of the antenna circuit. To tune the antenna circuit, the adjustable components of the antenna circuit are adjusted so that the electric voltage has a determined amplitude.

Systems and methods are described for a GPS receiver capable of functioning in the presence of interference. A method includes detecting an interfering signal including: tuning a band pass filter over a frequency range; and at each of a plurality of incremental frequencies: computing a set of band pass filter coefficients; sending the set of band pass filter coefficients to a digital filter; repeatedly transforming an analog-to-digital converter output having a quantization level in excess of 2 bits into a band pass filter output with the digital filter to obtain a plurality of samples; computing an average of the plurality of samples; and comparing the average to a threshold to detect peaks that exceed a threshold. An apparatus, comprising: an analog radio frequency circuit; an analog-to-digital converter coupled to the analog radio frequency circuit, the analog-to-digital converter providing a quantization level in excess of 2 bits; a digital filter coupled to the analog-to-digital converter; and a digital circuit coupled to the digital filter.

A method for detecting encoded digital data from a substantially sinusoidal waveform, the encoded digital data having one of a first value and a second value at selected phase angles θn comprises generating the waveform having an amplitude Y defined by a first function at phase angles lying outside of regions having a range Δθ beginning at each phase angle θn, said first function being Y=sin θ; generating the waveform having an amplitude Y defined by the first function at phase angles lying inside the regions having a range of Δθ beginning at each phase angle θn where data of the first value is to be encoded; and generating the waveform having an amplitude Y defined by a second function at phase angles lying inside the regions having a range of Δθ associated with each phase angle θn where data of the second value is to be encoded, the second function being different from Y=sin θ, the detection including deriving sync pulses from minima and maxima of the substantially sinusoidal waveform to frame data words.