338results about "Resonant circuits using central processing units" patented technology

It is determined, in accordance with a signal supplied by a tuner and indicating a signal reception state of the tuner, whether or not signal reception has been performed normally. Then, power supply to the tuner is stopped when it is determined that signal reception has not been performed normally. Further, it is detected whether or not an antenna has been connected to the tuner apparatus. Then, power supply to the tuner is stopped when it is determined that the antenna has not been connected to the tuner apparatus.

A tuner and a broadcasting signal receiver including the tuner. The tuner includes a band selection module that selects an RF broadcasting signal within the frequency band corresponding to a selected channel, and a low noise amplifier module that amplifies the signal with a specific received signal strength indicator (RSSI) to produce an RF broadcasting signal with a specific gain.

A tunable receiver is disclosed including a plurality of select filters to perform an initial band selection, a variable-gain low noise amplifier (LNA) whose gain is controlled to prevent its output power level to exceed a predetermined power threshold, a plurality of digitally-tunable tracking filters to pass signals within a selected channel and to reject signals in a corresponding image band, a second LNA to further amplify the received RF signal and to generate differential signal outputs, a down converting stage which converts the received RF signal to an IF signal while rejecting signals in the image band, an IF trap to further reject undesired signals present at the output of the down converting stage, an IF amplifier to amplify the IF signal to compensate for losses, an IF filter to provide channel select and reject undesirable signals, and a variable-gain IF amplifier to amplify the IF signal and maintain its power level within specification.

An integrated front end filter for a tuner provides an array of from several to a multitude of passbands, each for passing at least one but less than all channels designated in a band of frequencies. Each passband is exclusively selectable. The integrated front end filter can include at least one active filter unit with an active reactance element in either of fixed and variable filter configurations and a decoder coupled to said at least one active filter unit and being responsive to a control signal for selecting a one of the passbands. In one example, a multitude of active filter units of fixed filter configuration provide the multitude of passbands. In another example, a plurality of data corresponds to a like plurality of selectable passbands in combination with a filter element of the variable filter configuration. Each data is stored at a predetermined location and reproduced in response to a corresponding control data signal from a tuner controller. Each data characterizes one of the plurality of passbands. The filter element is switchable from one passband to another in response to the control data signal. Lower power dissipation and lesser requirements of an on-following integrated circuitry tuner permit a reduction of “off chip” connections and cost.

A tunable filter has a plurality of variable capacitors and a plurality of inductor elements, each being formed on a common substrate, a filter circuit formed by using at least a portion of the plurality of variable capacitors and a portion of the plurality of inductor elements, a monitor circuit formed by using at least a portion of the plurality of variable capacitors and a portion of the plurality of inductor elements, a detecting circuit which detects a prescribed circuit constant of the monitor circuit, a storage which stores information relating to a reference circuit constant of the monitor circuit, and a capacitance control circuit which controls capacitance of the variable capacitors in the monitor circuit and capacitance of the variable capacitors in the filter circuit, based on a result detected by the detecting circuit and information stored in the storage.

Systems and methods are described for a GPS receiver capable of functioning in the presence of interference. A method includes detecting an interfering signal including: tuning a band pass filter over a frequency range; and at each of a plurality of incremental frequencies: computing a set of band pass filter coefficients; sending the set of band pass filter coefficients to a digital filter; repeatedly transforming an analog-to-digital converter output having a quantization level in excess of 2 bits into a band pass filter output with the digital filter to obtain a plurality of samples; computing an average of the plurality of samples; and comparing the average to a threshold to detect peaks that exceed a threshold. An apparatus, comprising: an analog radio frequency circuit; an analog-to-digital converter coupled to the analog radio frequency circuit, the analog-to-digital converter providing a quantization level in excess of 2 bits; a digital filter coupled to the analog-to-digital converter; and a digital circuit coupled to the digital filter.

Methods and systems to implement and operate software-defined radios (SDRs). An SDR may be configured to perform a combination of fractional and integer frequency synthesis and direct digital synthesis under control of a digital signal processor, which may provide a set of relatively agile, flexible, low-noise, and low spurious, timing and frequency conversion signals, and which may be used to maintain a transmit path coherent with a receive path. Frequency synthesis may include dithering to provide additional precision. The SDR may include task-specific software-configurable systems to perform tasks in accordance with software-defined parameters or personalities. The SDR may include a hardware interface system to control hardware components, and a host interface system to provide an interface to the SDR with respect to a host system. The SDR may be configured for one or more of communications, navigation, radio science, and sensors.

A broadband integrated receiver for receiving input signals and outputting composite video and audio signals is disclosed. The receiver employs an up-conversion mixer and a down-conversion mixer in series to produce an intermediate signal. An intermediate filter between the mixers performs coarse channel selection. The down-conversion mixer may be an image rejection mixer to provide additional filtering.

A system for synchronizing a second receive chain relative to a first receive chain in a multi-mode communication system. The system includes a first circuit that measures a first frequency associated with the first receive chain. A second circuit adjusts a second frequency associated with the second receive chain based on the first frequency and provides a desired second frequency to the second receive chain in response thereto. In a specific embodiment, the first circuit includes a first counter that receives a signal associated with an output of a first oscillator and provides a measurement of the first frequency in response thereto. The second circuit includes a frequency synthesizer for providing the desired second frequency in response to a frequency control or reference signal. Another circuit generates the control or reference signal based on a difference between the second frequency and the first frequency. A second counter receives a signal characterized by the second frequency and provides the second frequency in response thereto.

A method and apparatus for calibrating a reference oscillator and use of a calibrated reference oscillator is disclosed. To gain cost reduction advantages, a less accurate reference oscillator is utilized in a wireless communication device. The cost benefit is gained at the expense of reference oscillator accuracy in that its inability to generate a signal with a highly accurate reference frequency inhibits acquisition of a carrier or pilot signal. To compensate, a correction factor is generated by minimizing the difference between the reference oscillator signal and a signal of known frequency, such as an external reference signal. Access to the reference oscillator signal, or a signal related thereto, may be gained via the communication device antenna or a test port. The correction factor may be stored in the wireless communication device for use in conjunction with the reference oscillator to thereby generate the highly accurate reference signal at the reference frequency.

A receiver (1100) includes a direct digital frequency synthesizer (130), a mixer (105), and a clock source (1110, 1130). The direct digital frequency synthesizer has an input terminal for receiving a first clock signal at a first frequency, and an output terminal for providing a digital local oscillator signal synchronously with the first clock signal. The mixer (105) has a first input terminal for receiving a radio frequency (RF) signal, a second input terminal coupled to the output terminal of the direct digital frequency synthesizer (130), and an output terminal for providing an IF signal having a spectrum centered about a selectable one of a plurality of center frequencies. The clock source (1110, 1130) has an output terminal for providing the first clock signal without using any harmonic frequency that overlaps the spectrum for any of the plurality of center frequencies.

A method and apparatus for compensating an oscillator in a location-enabled wireless device is described. In an example, a mobile device includes a wireless receiver for receiving wireless signals and a GPS receiver for receiving GPS signals. The mobile device also includes an oscillator having an associated temperature model. A frequency error is derived from a wireless signal. The temperature model is adjusted in response to the frequency error and a temperature proximate the oscillator. Frequency error of the oscillator is compensated using the adjusted temperature model. In another example, a frequency error is derived using a second oscillator within the wireless receiver.

In various embodiments, the invention provides a discrete clock generator and / or a timing and frequency reference using an LC-oscillator topology, having a frequency controller to control and provide a stable resonant frequency, which may then be provided to other, second circuitry such as a processor or controller. Frequency stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages. The controlled reactance modules may include fixed or variable capacitances or inductances, and may be binary weighted. Arrays of resistive modules are also provided, to generate one or more control voltages.

In various embodiments, the invention provides a clock generator and / or a timing and frequency reference using an LC-oscillator topology, having a frequency controller to control and provide a stable resonant frequency, which is integrated with other, second circuitry such as a processor or controller. Frequency stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages. The controlled reactance modules may include fixed or variable capacitances or inductances, and may be binary weighted. Arrays of resistive modules are also provided, to generate one or more control voltages.

In various embodiments, the invention provides a clock generator and / or a timing and frequency reference using an LC-oscillator topology, having a frequency controller to control and provide a stable resonant frequency, which is integrated with other, second circuitry such as a processor or controller. Frequency stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages. The controlled reactance modules may include fixed or variable capacitances or inductances, and may be binary weighted. Arrays of resistive modules are also provided, to generate one or more control voltages.

A resonant circuit tuning system and a method for tuning are provided. The resonant circuit tuning system may include an LCR circuit and a reactive element magnetically coupled to the LCR circuit.

An antenna circuit tunable to a determined resonance frequency, includes an antenna coil and adjustable components. The antenna circuit includes a filter having at least one point to tap an electric voltage the amplitude of which forms a pertinent indication for the tuning of the antenna circuit. To tune the antenna circuit, the adjustable components of the antenna circuit are adjusted so that the electric voltage has a determined amplitude.

A method for correcting frequency errors in the local reference frequency crystal oscillator of a GPS receiver begins with a step in which the ordinary temperature response of a crystal is characterized. A hardware circuit is incorporated with that crystal to mirror that same characteristic. A temperature sensor is used to control a compensation applied. The combination outputs a fairly flat temperature response, e.g., near zero delta-frequency change over the operating temperature range. But this flat response has an unknown offset from the true frequency. A next step finds a precision timing reference, such as when the receiver locks onto and tracks GPS satellites. The receiver then knows time precisely and a navigation software can compute the offset accurately. A value is stored for that offset in memory. Such value is thereafter recalled at each cold start and is used by software to remove the expected frequency offset.

A millimeter wave band communication apparatus includes a millimeter wave band transmitter receiving a plurality of input modulation signal waves to transmit a millimeter wave band multiplex signal wave, and a millimeter wave band receiver receiving the transmitted millimeter wave band multiplex signal wave to restore the plurality of input modulation signal waves. The millimeter wave band transmitter includes a frequency arranging circuit generating a multiplex signal wave having respective frequency bands of the plurality of input modulation signal waves arranged on the frequency axis independent of each other, a frequency up-converter up-converting the generated multiplex signal wave to the millimeter wave band, and a transmission circuit transmitting the millimeter wave band multiplex signal wave. The millimeter wave band receiver includes a reception circuit receiving the millimeter wave band multiplex signal wave, a frequency down-converter down-converting the millimeter wave band multiplex signal wave from the millimeter wave band, and a frequency rearranging circuit restoring the down-converted multiplex signal wave into the plurality of input modulation signal waves respectively having the former frequency bands.

An RF-to-IF converter includes radio frequency (RF) to intermediate frequency (IF) processing circuitry and a frequency synthesizer for generating a local oscillator signal and clocking signals. The frequency synthesizer includes a local oscillator (LO) output coupled to the processing circuitry, a baseband processor clock output, and clock generation circuitry for generating a baseband processor clock with a frequency of approximately 48 fo on the baseband processor clock output, where fo is 1.023 MHz.

Embodiments may be used to control a controllable element that has a nonlinear but monotonic relationship with a control value. In such embodiments, a system may perform control by receiving an error value corresponding to an error of an output signal from the controllable element, and determining the control value within two iterations of a Newton (Secant) algorithm, where the control value enables generation of the output signal within a predetermined tolerance to a nominal value for the control signal.

A communication semiconductor integrated circuit has an oscillator circuit forming part of a transmission PLL circuit fabricated on a single semiconductor chip together with an oscillator circuit forming part of a reception PLL circuit and an oscillator circuit for an intermediate frequency. The oscillator circuit for the transmission PLL circuit is configured to be operable in a plurality of bands. The communication semiconductor integrated circuit also comprises a circuit for measuring the oscillating frequency of the oscillator circuit for the transmission PLL circuit, and a storage circuit for storing the result of measurement made by the measuring circuit. A band to be used by the oscillator circuit for the transmission PLL circuit is determined based on values for setting the oscillating frequencies of the oscillator circuit forming part of the reception PLL circuit and the intermediate frequency oscillator circuit, and the result of measurement stored in the storage circuit.

Frequency conversion into a first intermediate frequency which is higher than a received frequency band is performed for a received signal by using a mixer and a PLL. Next, an output of the mixer is frequency converted into a second intermediate frequency of a base band by using a quadrature mixer formed by mixers and a phase shifter. At this time, a frequency of the local oscillation signal of a PLL supplied to the quadrature mixer is controlled so as to be switched, depending on a position of the received segment, between a frequency which is higher than the first intermediate frequency and a frequency which is lower than the same.

A novel and useful apparatus for and method of spur reduction using computation spreading in a digital phase locked loop (DPLL) architecture. A software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU is adapted to spread the computation of the atomic operations out over and completed within an entire PLL reference clock period. Each computation being performed at a much higher processor clock frequency than the PLL reference clock rate. This functions to significantly reduce the per cycle current transient generated by the computations. Further, the frequency content of the current transients is at the higher processor clock frequency. This results in a significant reduction in spurs within sensitive portions of the output spectrum.

In a cellular phone terminal, the transmitter, receiver, and combiner consist of common hardware that can be used in multiple communication systems. The channel CODEC, modulator, equalizer, and memory for signal processing programs consist of common hardware that performs signal processing supporting multiple communication systems. The CPU and the memory for the communication control program support different communication control systems, thus providing a multi-mode cellular phone terminal supporting different communication systems with simple design and low cost.

An antenna circuit tunable to a determined resonance frequency, includes an antenna coil and adjustable components. The antenna circuit includes a filter having at least one point to tap an electric voltage the amplitude of which forms a pertinent indication for the tuning of the antenna circuit. To tune the antenna circuit, the adjustable components of the antenna circuit are adjusted so that the electric voltage has a determined amplitude.