46results about How to "Relevant" patented technology

The embodiment of the invention discloses an application display method and a terminal device. The application display method comprises the steps of: detecting a started application in a terminal; judging whether the started application is a preset application, wherein the preset application is an application comprising at least one display interface; and if the started application is the preset application, acquiring a first display interface and a second display interface of the started application and respectively displaying the first display interface and the second display interface on a first display screen and a second display screen of the terminal. According to the application display method and the terminal device which are disclosed by the embodiment of the invention, by respectively displaying a plurality of display interfaces of the same preset application on the first display screen and the second display screen of the terminal, displayed contents on the two display screens of the terminal are relatedand have strong interactivity, so that the advantages of the double-display-screen terminal are sufficiently reflected.

The invention discloses a blood-production preparation quality test method which comprises the following steps: (1) preparation of a comparison product solution; (2) preparation of a test sample solution; (3) chromatographic conditions: a chromatographic column is C18 reversion phase chromatographic column; gradient elution is adopted, and a flowing phase is a gradient elution solution composed of acetonitrile and 0.1-0.2 percent of a phosphoric acid solution; the detection wavelength is 200-230 nanometers; the column temperature is 25-40 DEG C; the flowing speed is 0.8ml / min-1.2ml / min; the analysis lasts for 60 min; and (4) testing: the fingerprint spectrum is obtained through efficient liquid phase chromatography. The testing method provided by the invention is simple to operate, characteristic components are completely retained, and the testing method is good in repeatability and stability, high in precision and strong in specificity.

The invention provides a combined-type anti-counterfeiting mark based on a same ID. The combined-type anti-counterfeiting mark is composed of a quick response code and a raster graph. The quick response code and the raster graph all comprise the same ID number extracted from an ID number database during a generating process. The method for generating the combined-type anti-counterfeiting mark comprises the steps that by using a quick response code generator, the ID number, parameter information of the quick response code, plaintext information and preset ciphertext information memory area are converted into the quick response code, wherein the ID number, the parameter information of the quick response code and the plaintext information are extracted from the ID number database; by using a raster graph generator, the raster graph is generated by the ID number which is same as the quick response code. The device for generating the combined-type anti-counterfeiting mark comprises the quick response code generator and the raster graph pattern generator. The quick response code and the raster graph comprise the same ID number, and therefore the quick response code and the raster graph have relevancy, due to the fact that quick response code can only be recognized and read through dedicated equipment, the raster graph cannot be recognized once again after being copied and scanned, and therefore the high level anti-counterfeiting performance is achieved.

The present application provides a zero-knowledge proof circuit optimization method, device, terminal equipment, and storage medium, the method including: constructing an abstract syntax tree of an initial zero-knowledge proof circuit; optimizing the initial circuit constraints of an initial zero-knowledge proof circuit according to the abstract syntax tree ; The optimized initial circuit constraints are correlated and classified to obtain circuit constraints of different classifications of the zero-knowledge proof circuit, and the circuit constraints of different classifications are run in parallel in the zero-knowledge proof circuit. The zero-knowledge proof circuit optimization method provided by this application can optimize the original circuit constraints in the zero-knowledge proof circuit, eliminate some unnecessary circuit constraints in the zero-knowledge proof circuit, and reduce the possibility of circuit constraint errors. At the same time, corresponding association is made to the optimized circuit constraints, so that the associated circuit constraints have context relevance, and the operating efficiency is improved.