38results about How to "Reduce the amount of jitter" patented technology

A multiplexer circuit, system and method is provided herein for multiplexing signals with reduced jitter by eliminating all crosstalk and power supply noise injection within the multiplexer circuit. For example, crosstalk and supply noise injection may be eliminated by: (i) separating the multiplexing function into three separate logic gates and (ii) allowing only one switching input per logic gate. In some cases, jitter may be further reduced by distributing the logic gates across three distinct power domains. In other words, the logic gate inputs may be further isolated by gating each signal in its own power domain. In addition, the multiplexer circuit provides built in delay matching by utilizing three substantially identical logic gates.

A distributed avionics system arranged in an aerial vehicle for controlling at least one avionics function. A plurality of avionics processing subsystems are interconnected in a network. Each avionics processing subsystem includes a processor arranged to process at least one task so as to provide a set of data messages including at least one unit of data related to controlling the at least one avionics function on basis of provided input data, related to conditions of the at least one avionics function. A memory module is in operative connection with the processor and is arranged to store instructions for the processor to process the at least one task. At least one of the avionics processing subsystems is arranged to transmit at least one synchronization cycle start signal onto the network.

A controllable delay line includes an anti-jitter unit, a dependent current source, a first current mirror, a second current mirror, a regulation capacitor, a compensation capacitor and an output buffer unit. The anti-jitter unit receives a first bias voltage and produces a second bias voltage based on the first bias voltage. When the voltage source used in the controllable delay line has a variation, the second bias voltage varies therewith. The regulation capacitor is used for reducing the variation of the voltage difference between the voltage source and a node voltage of the first current source. The compensation capacitor is used for reducing the influence of a transition of the input signal of the output buffer unit on the node voltage, so as to lower the jitter amount of the output signal of the output buffer unit.

A clock distribution network having a separate power supply for top levels thereof is disclosed. In one embodiment, an integrated circuit includes a clock distribution network configured to distribute a clock signal to each of a number of clock consumers. The clock distribution network is arranged in a hierarchy of levels, with each of the levels including at least one buffer, and with the upper levels being closer to a source of the clock signal and the lower levels being closer to the clock consumers. The buffers of the upper levels are coupled to receive power from a first power source, via a first power grid. The buffers of the lower levels are coupled to receive power from a second power source, separate from the first, via a second power grid.

The invention discloses a marine escalator, which belongs to the technical field of marine equipment. The device of the invention includes: a bottom plate installed at an inclination, both ends of the bottom plate are fixed with a connecting base body, shock absorbing components are superimposed on the bottom of the bottom plate to support the bottom surface of the bottom plate, and Filling blocks are also filled between the shock assembly and the bottom surface of the bottom plate. The shock absorption assembly includes a box body, a second rubber body is placed inside the box body, and a first stud bolt is connected to the second rubber body. The end of the first stud bolt A horizontally arranged top plate is connected, and an expansion plate is arranged on the top of the top plate to seal the upper port of the box body, and a connecting sleeve is sleeved on the outside of the first stud bolt between the top plate and the second rubber body. The present invention reduces the vibration of the escalator during the swaying process of the ship body by arranging a shock-absorbing assembly under the escalator, and improves the stability of the escalator.

The invention discloses a pipeline pressure testing system and method.The pipeline pressure testing system comprises a water feeding pump, a pressurizing pump, pressure testing pipelines, fixing pieces, a safety valve return pipe, and a pressure-resisting distribution pipe with an inlet connected with the pressurizing pump and the water feeding pump.The pressure-resisting distribution pipe is communicated with a plurality of connecting pipes, two ball valves and a safety valve are arranged on each connecting pipe in sequence, and the tail end of each connecting pipe is connected with the corresponding pressure testing pipeline.The pipeline pressure testing method includes the steps that firstly, the pressure-resisting distribution pipe and the safety valve return pipe are fixed; then, water is fed into the pressure testing pipelines under the action of control valves and the ball valves; the pressure testing pipelines are pressurized after water feeding is finished.By means of the pipeline pressure testing system and method, simultaneous water feeding and pressurizing at different pressure grades are achieved, and thus the labor intensity of workers is relieved; all steps achieve the mutual effect in the pressure testing process, and thus pressure testing accuracy is improved; meanwhile, the service life of equipment is effectively prolonged, and the later-period maintenance cost is reduced.

The invention discloses a dynamic data acquiring system and a method for precisely positioning an acquiring position thereof. The dynamic data acquiring system comprises an FPGA controller, a step motor, a driving circuit of the step motor, and a position sensor. An FPGA controlling circuit sends direction and pulse signals to the driving circuit of the step motor and maintains a position counter. The driving circuit of the step motor receives driving pulses and direction signals and drives the step motor to move. In the moving process of the step motor, when the FPGA detects that the position sensor has the effective jump, the FPGA resets the position counter, and the position counter counts the sent pulses; after a sent pulse number reaches the set position pulse number of acquiring points and the effective condition of the pulses is detected, the data acquiring operation is carried out. The invention has the advantages of accurate positioning of the acquiring points, high real-timeperformance, automatic control, simplicity, reliability and lower cost.

The invention provides a rotating shaft structure applied to a glass turnover device and further provides the glass turnover device. The rotating shaft structure comprises a rotating shaft body. The rotating shaft body is internally provided with a cavity; at least one through hole set is formed in the surface of the rotating shaft body; each through hole set comprises two oppositely-formed through holes, wherein the two through holes are located in the surfaces of the two opposite sides of the rotating shaft body correspondingly; and the through holes are strip-shaped holes extending in the axial direction of the rotating shaft body, the height of each through hole is 8-16 mm, and the wall thickness of the rotating shaft body is 21-35 mm. Compared with the prior art, through the rotatingshaft structure applied to the glass turnover device, the requirement of turning-over of glass and the requirement of horizontal passing of the glass can be met simultaneously.

The invention discloses a driver and a method for outputting a low-jitter serial signal. The driver comprises a data time sequence adjusting module, a pre-driver, and an output driver. The data time sequence adjusting module is used for receiving clock signals ckp and ckn generated by a system circuit, even-bit data de, and odd-bit data do, and performing logic gate operation processing in order to output data de_smp and do_smp. The pre-driver is used for receiving the data de_smp and do_smp outputted by the data time sequence adjusting module and the clock signals ckp and ckn generated by the system circuit, and performing logic gate operation processing in order to output data dep, data dop, data den, and data don. The output driver is used for receiving the data dep, the data dop, the data den, and the data don outputted by the pre-driver and performing logic gate operation in order to output a low-jitter serial signal dos. The driver and the method for outputting a low-jitter serial signal finally output a low-jitter serial signal by means of reasonable circuit structural design.

The invention discloses a kind of optical disk data accessing device, has an optical head tilt control module, which is used to control the tilt quantity, decreases flutter of regenerate signal. The optical tilt control module includes regenerate signal generating unit, which is used to receive the radio frequency signal generated by the optical head, and generates EFM signal; flutter examining device, receives EFM signal, and examines the flutter of EFM signal; tilt control unit, which is used to correct tilt control value, and selects better value, in adjusting period it generates the tilt control value according to regenerate data; and tilt driver for receiving tilt control value and generates tilt control signal to drive optical head to rotate.