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Driver and method for outputting a low-jitter serial signal

A driver and pre-driver technology, applied in the direction of logic circuit with logic function, logic circuit coupling/interface using field effect transistor, logic circuit connection/interface layout, etc., can solve the problem of large amount of serial signal jitter, etc.

Active Publication Date: 2014-05-21
珠海妙存科技有限公司
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Problems solved by technology

[0008] Based on the above problems, the present invention provides a driver and a low-jitter serial signal output method, which overcomes the technical defect that the serial data in the prior art has a large amount of jitter output by the existing driver.

Method used

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  • Driver and method for outputting a low-jitter serial signal
  • Driver and method for outputting a low-jitter serial signal
  • Driver and method for outputting a low-jitter serial signal

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Embodiment Construction

[0060] The specific implementation of a driver and a method for outputting a low-jitter serial signal of the present invention will be described below with reference to the accompanying drawings.

[0061] The embodiment of the present invention provides a driver. The driver provided in the embodiment of the present invention is described in detail by taking a voltage mode driver as an example, but not limited thereto. The driver 2 is integrated in a system circuit 1, see figure 2 and Figure 2a , the driver 2 includes a data timing adjustment module 3, a pre-driver 4 and an output driver 5, wherein:

[0062] The data timing adjustment module 3 is used to receive the clock signals ckp and ckn generated by the system circuit, the even-number data de and the odd-number data do, and perform logic gate operation to process the output data de_smp and do_smp;

[0063] The pre-driver 4 is used to receive the data de_smp and do_smp output by the data timing adjustment module and the ...

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Abstract

The invention discloses a driver and a method for outputting a low-jitter serial signal. The driver comprises a data time sequence adjusting module, a pre-driver, and an output driver. The data time sequence adjusting module is used for receiving clock signals ckp and ckn generated by a system circuit, even-bit data de, and odd-bit data do, and performing logic gate operation processing in order to output data de_smp and do_smp. The pre-driver is used for receiving the data de_smp and do_smp outputted by the data time sequence adjusting module and the clock signals ckp and ckn generated by the system circuit, and performing logic gate operation processing in order to output data dep, data dop, data den, and data don. The output driver is used for receiving the data dep, the data dop, the data den, and the data don outputted by the pre-driver and performing logic gate operation in order to output a low-jitter serial signal dos. The driver and the method for outputting a low-jitter serial signal finally output a low-jitter serial signal by means of reasonable circuit structural design.

Description

technical field [0001] The invention relates to the technical field of communication, in particular to a driver and an output method of a low-jitter serial signal. Background technique [0002] With the rapid development of the electronic information industry, especially the development of portable electronic devices, the speed of data processing and transmission is increasing day by day. The types of high-speed serial interfaces emerge in endlessly. The transmission speed of serial signals has reached several Gbps or even tens of Gbps. With the continuous improvement of data transmission rate in communication systems, the jitter problem in high-speed serial systems is becoming more and more serious. The impact of jitter on the system The impact multiplies as the data transfer rate increases. When the data transmission rate exceeds Gbps, the jitter becomes the key factor to determine the system performance. When the jitter is relatively large, there may be phenomena such a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/0185H03K19/20
Inventor 倪陈志王洪魁
Owner 珠海妙存科技有限公司
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