31results about How to "Improve phase detection accuracy" patented technology

The invention discloses a microwave phase detection device based on microwave photon technology, comprising: a light source for providing an optical pulse sequence with a pulse width of femtosecond level; The Sagnac ring structure is used to phase-modulate the two microwave signals whose frequency is an integer multiple of the repetition frequency of the optical pulse sequence on the two orthogonal polarization states of the optical pulse sequence, and make the forward and backward modulated optical signals in the Sagnac The output port of the ring structure forms interference; the polarization separation module is used to separate the two orthogonal polarization states of the two optical signals output by the Sagnac ring structure; the balance detection module is used to separate the two separated horizontal and The two vertically polarized optical signals are detected in balance, and the phases of the two microwave signals are respectively obtained. The invention also discloses a microwave phase-locking device based on microwave photon technology. The invention can independently and accurately detect the phases of two microwave signals at the same time, and has simple structure and low implementation cost.

The invention discloses a clock phase discrimination device and method, which are used for measuring the phase difference between a reference signal and a signal to be measured; both need to obtain a phase signal to be measured that can reflect the phase difference between the reference signal and the signal to be measured. The number of phase detection clock signals that can be accumulatively accommodated within the phase width of the phase signal to be measured; and by symmetrically integrating the continuous phase detection clock signal, the integration result of the digital quantity phase detection clock signal within the phase width of the phase signal to be measured is obtained, and then Obtain the phase value of the phase detection clock signal when the integration result of the phase detection clock signal is obtained; then, calculate the phase of the phase detection signal according to the obtained phase value of the phase detection clock signal and the accumulated number of phase detection clock signals width. The device and method of the invention can significantly improve the precision of clock phase discrimination.

The present invention proposes a combined phase detection and tracking loop of a phase-locked loop and a subcarrier loop, including a carrier tracking loop, a subcarrier tracking loop, and a spread code tracking loop, wherein the carrier tracking loop first conducts a process on the received intermediate frequency BOC signal Carrier stripping processing, the obtained output signal is used as the input of the subcarrier tracking loop, multiplied by the local cosine and sine signals generated by the subcarrier numerical control oscillator, and the obtained signal is input into the spread spectrum code tracking loop for code phase tracking, for binary For the ambiguity problem of offset carrier signal tracking, a joint phase detection method is used in the joint tracking loop of carrier tracking loop and subcarrier tracking loop to solve the phase ambiguity problem caused by noise when the signal-to-noise ratio is low. The method improves the accuracy of phase detection and realizes precise tracking.

The invention relates to an anti-multipath high-precision code loop phase detection method. The anti-multipath high-precision code loop phase detection method comprises steps that a shift register is constructed, and the shift register is used to generate four different relatively delayed local codes; by using a narrow correlator technology, an integral accumulated value of a same-direction component and an orthogonal component is calculated; a code phase difference is calculated respectively by adopting a non-coherent early minus late amplitude method and a front and back slope method, and the switching of the above mentioned two phase detection methods is carried out according to the phase difference. The anti-multipath high-precision code loop phase detection method is advantageous in that anti-multipath effect and high phase detection result precision are provided; the accurate phase difference is calculated, and the local codes are aligned with received codes more accurately, and therefore the tracking precision of the code loop and a positioning performance of a receiver are improved.

This invention relates to a high-frequency clock jitter measuring circuit and calibration method thereof, which comprises a first / second oscillation signal unit to generate the first / second oscillation signal with TV1 / TV2 period (TV1 G01R 29 / 02 G01R 23 / 02 G01R 31 / 00 H03K 5 / 19 6 13 4 2006 / 4 / 18 1837835 2006 / 9 / 27 100501423 2009 / 6 / 17 2009 / 6 / 17 2009 / 6 / 17 Peking University Shenzhen Graduate School 518057 Zhang Jingkai Li Chongren Yu Fei Tian Chao guo yan 44223

The invention relates to the technology of ultrasonic power supplies and provides constant-power power supply with a high power factor and fast response to reduce system complexity and improve detection precision. To this end, the invention provides a constant-power driving power supply based on an ARM and a multiplier and a driving method, The constant-power driving power supply comprises a firstpart which is a driving circuit including a DDS chip, an integrated PWM wave control chip and an inversion amplification circuit; a second part which is a sampling matching circuit; a third part which is a signal conditioning circuit; and a fourth part which is a micro-control module formed by an ARM microprocessor and achieving constant-power control by adjusting the frequency and the duty ratioof a PWM wave. The invention is mainly applied to the design and manufacture of ultrasonic power supplies.

The invention relates to a method for detecting vibroseis signal phases based on K-L decomposition. When a vibroseis works, excitation signals of a vibroseis are acquired in real time through a sensor installed on the vibroseis, high random noise of the signals is removed through a K-L decomposer, and the signals are sent to a phase detector and a phase controller respectively to conduct phase detection and phase control on the vibroseis excitation signals. Compared with an existing filtering method, phase information of original signals is not lost in the vibroseis excitation signals extracted by adopting the K-L decomposition method, and the K-L decomposition method especially has the good suppressing effect on signal bands with the high random noise; compared with a self-adaptive filtering method, a mathematic model does not need to support the method for detecting the vibroseis signal phases based on K-L decomposition, and the method can be excellently suitable for unknown coupling model environment; the signals extracted by adopting the K-L decomposition method can truly reflect phase information of the vibroseis excitation signals, the problem of zero point hopping in zero crossing point phase detection is solved, and accuracy of phase detection of the vibroseis excitation signals is improved.

The invention discloses a digital phase detector for GPS taming crystal oscillator, comprising: a 2N frequency divider for obtaining a square wave pulse signal with a cycle of 2N seconds by dividing the frequency of the 1Hz PPS signal output by the GPS module; High and low level pulse width counters for wide counting; the input is connected to the externally provided frequency lock enable signal, connected to GPS and frequency-divided OCXO clock to output the second pulse clock of the internal second pulse signal; input the internal second pulse signal and GPS module output PPS signal, count the time difference between the rising edges, and output the phase difference counter clock of the phase difference count value; it is used to realize the OCXO crystal oscillator tracking the frequency of the GPS PPS signal, and simultaneously output the frequency value and the frequency count value latch of the phase error value register and a phase error value latch. The invention is convenient for timing design, and avoids the fuzzy problem of leading and lagging initial phase errors. The frequency and phase measuring counter adopts a serial counter scheme, so that the counting clock frequency is not affected by the number of counting digits.

The invention relates to a vibroseis phase-locked control system which is formed by that a main control unit is respectively connected with a phase-locked control unit and a signal acquisition and output unit which is connected with a vibroseis module. A K-L decomposition filter is realized in an FPGA chip through programming, the influence of an external electromagnetic interference noise on a phase-locked loop is avoided, the anti noise performance of the system is raised, the zero phase shifting filtering of a vibroseis feedback signal is realized, the problems of feedback signal phase detection time offset and zero jump are solved, thus the phase detection accuracy is improved significantly, and the phase accuracy of a phase-locked loop output signal is increased. At the same time, according to the system, a standard signal is generated by a direct frequency synthesizer (DDS), and compared with the existing analog phase-locked loop control scheme, according to the phase control scheme with the combination of the direct frequency synthesizer and digital phase-locked loop technology, the speed of vibroseis phase-locked control is greatly improved.

The invention provides a lead-lag digital phase discriminator structure which is composed of a first signal path, a second signal path and a three-input NAND gate. The first signal path comprises a first D-trigger, a first phase inverter, a first buffer, a first NAND gate, a first digital pulse amplifier and a third D-trigger. The second signal path comprises a second D-trigger, a second phase inverter, a second buffer, a second NAND gate, a second digital pulse amplifier and a fourth D-trigger. The third input end of the three-input NAND gate is connected with an input enabling signal, and the output end is connected with the reset ends of the first and second D-trigger. Effective time of a trigger signal is increased via appropriate additional arrangement of certain logic units and triggers so that lead-lag phase discrimination precision can be greatly enhanced.