The invention relates to a reset circuit, which comprises a power-on reset circuit and a power-off reset circuit, wherein the power-on reset circuit comprises a first field-effect tube, a second field-effect tube, a third field-effect tube, a first two-input NAND gate, a second two-input NAND gate, a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, an OR gate, a first capacitor, a second capacitor and a buffering delay module; and the power-off reset circuit comprises fourth to tenth field-effect tubes, a fifth NOT gate and a buffering module. The reset circuit can well execute a reset function, is simple, low in cost and high in electro magnetic compatibility (EMC), can be widely used in integrated circuits, particularly integrated circuits with strict requirements on cost control such as infrared circuits, as well as most microprogrammed control units (MCUs) and circuits with high requirements on anti-interference performance and EMC performance.