38results about How to "Eliminate skew" patented technology

An electrical interconnection system with high speed, differential electrical connectors. The connector is assembled from wafers each containing a column of conductive elements, some of which form differential pairs. Skew control is provided for at least some of the pairs by providing a profile on an edge of the shorter signal conductor of the pair. The profile may contain multiple curved segments that effectively lengthen the signal conductor without significantly impacting its impedance. For connectors in which ground conductors are included between adjacent pairs of signal conductors, patterned segments of varying parameters may be included on edges of the signal conductors and ground conductors to equalize electrical lengths of all edges in a set of edges for which there is common mode or differential mode coupling as a signal propagates along each pair. Such features for skew control may be used in combination with other skew control features. The features used may vary depending on the location of the pair within the column.

Systems and methods of verifying the results of an initial image recognition process are presented. A verification engine can receive a set of candidate images corresponding to the results of an image recognition process performed on a captured query image. The verification engine can determine an appropriate verification technique to apply to the images of the candidate set, and classify, re-rank or otherwise re-organize the candidate set such that the best match from the candidate set is confirmed as a proper match.

Various embodiments of methods and systems for providing virtual leaf driver nodes in a clock tree to drive a clock grid of an integrated circuit are disclosed. An integrated circuit may include a large number of clocked elements such as registers, flip-flops, etc. whose operation is synchronized by one or more clocks. For example, an operation performed by circuitry on one side of the die may need to occur at precisely the same time as another operation performed by circuitry on the other side of the die. In order to assure synchronicity of these events, a clock grid may be provided in the IC that is driven by virtual leaf driver nodes. The clock tree driving the clock grid may include a tier of leaf buffers. The output of a leaf buffer may be split, and the branches of the output connected to separate points on the clock grid.

A two-stage pixel skew compensation circuit for use with digital display monitors. The first stage of the compensation circuit aligns the edges of the pixels received on the color component signal lines of an analog video signal. The second stage of the de-skew compensation circuit realigns the pixels themselves so that no skew exists between the digitized video color components. The digitized video signals drive a digital video monitor.

The embodiment of the invention discloses a method, a site and a system for compensating transmission delay deviations among synchronous transmission channels. The method comprises the following steps: a source-end site resolves high-speed signals into multiple low-speed signals and sends the low-speed signals to an intermediate site, wherein each resolved low-speed signal includes an alignment identification; the intermediate site compares the transmission delay deviations of the received multiple low-speed signals based on the alignment identification, and aligns and sends the multiple low-speed signals; a destination-end site compares the received transmission delay deviations of the received multiple low-speed signals based on the alignment identification, aligns the multiple low-speed signals, and recovers the high-speed signals, so that the transmission delay deviations among synchronous transmission channels can be well eliminated, and the transmission delay deviations among synchronous transmission channels can be still eliminated under the condition of passing through multiple intermediate sites.

An electrical interconnection system with high speed, differential electrical connectors. The connector is assembled from wafers each containing a column of conductive elements, some of which form differential pairs. Skew control is provided for at least some of the pairs by providing a profile on an edge of the shorter signal conductor of the pair. The profile may contain multiple curved segments that effectively lengthen the signal conductor without significantly impacting its impedance. For connectors in which ground conductors are included between adjacent pairs of signal conductors, patterned segments of varying parameters may be included on edges of the signal conductors and ground conductors to equalize electrical lengths of all edges in a set of edges for which there is common mode or differential mode coupling as a signal propagates along each pair. Such features for skew control may be used in combination with other skew control features. The features used may vary depending on the location of the pair within the column.

A method for forming a metal programmable integrated circuit that can use a plurality of clock sources and balance clock skew. The integrated circuit has a semiconductor body. The method includes step (a) used for forming a plurality of basic units on the semiconductor body wherein each basic unit has at least a logic module, at least a driving module, and at least a storage module, and step (b) used for forming a metal layer for programming the logic module to be able to perform logic operations, programming the driving module to able to drive an input signal inputted into the driving module, and programming the storage module to be able to store data after performing step (a).

A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data including a pattern similar to actually transmitted data, a phase detecting unit which receives the edge information from the edge information storage unit and the pseudo data from the pseudo data pattern generating unit to detect a phase difference between the data and the clock signal and generate a corresponding detection result, and a phase control unit which controls a phase of the clock signal according to the corresponding detection result from the phase detecting unit, so as to eliminate a per-data input / output pin skew in a data write and read operation of the semiconductor memory device.

In an image forming apparatus that outputs a reference clock, divides the outputted reference clock based on a set multiple, and generates an image clock based on the division, a width of a synchronization signal that indicates dynamic deviation characteristics is detected, and the multiple is set in accordance with the detected width of the synchronization signal.

In an image forming apparatus that outputs a reference clock, divides the outputted reference clock based on a set multiple, and generates an image clock based on the division, a width of a synchronization signal that indicates dynamic deviation characteristics is detected, and the multiple is set in accordance with the detected width of the synchronization signal.

The present invention discloses a semiconductor memory device and a method for arranging signal lines thereof. The semiconductor memory device including a first memory cell array, an IO control circuit and a second memory cell array arranged between the first memory cell array and the IO control circuit, includes: first IO signal lines for transmitting data between the first memory cell array and the IO control circuit, wherein the first IO signal lines are connected to first data loading locations of the first memory cell array and extend in a straight line to the IO control circuit; and second IO signal lines for transmitting data between the second memory cell array and the IO control circuit, wherein the second IO signal lines are connected to first data loading locations of the second memory cell array and extend to the IO control circuit, wherein lengths of the first IO signal lines starting from the first data loading locations of the first memory cell array to the IO control circuit are identical to lengths of the second IO signal lines starting from the first data loading locations of the second memory cell array to the IO control circuit.

A semiconductor device includes a plurality of synchronization clock generators configured to generate a plurality of synchronization clock signals by mixing phases of first and second source clock signals having an identical frequency, a first clock transmission path configured to sequentially apply the first source clock signal to the plurality of synchronization clock generators by transferring the first source clock signal in a forward direction, a second clock transmission path configured to sequentially apply the second source clock signal to the plurality of synchronization clock generators by transferring the second source clock signal in a backward direction, and a plurality of data output units configured to synchronize a plurality of data with the plurality of synchronization clock signals and outputting the synchronized plurality of data.

The invention discloses an LED device capable of uniformly reflecting a light ray. The LED device comprises a light-emitting diode unit, a drive circuit board, a light-reflecting cover and an isolation gasket, wherein the isolation gasket is arranged between the drive circuit board and the light-reflecting cover, and a part reservation hole is arranged in the middle position of the isolation gasket; the light-emitting diode unit is used for penetrating through the part reservation hole and then is arranged on the drive circuit board; an opening is arranged in the light-reflecting cover; the inner diameter of the opening is the same as the outer diameter of the light-emitting diode unit; and the light-emitting diode unit is arranged in the opening of the light-reflecting cover. The LED device is capable of uniformly reflecting a light source generated by light-emitting diodes.

An apparatus and method of aligning a vehicle's fixed rear axle relative to the vehicle frame and suspension elements uses an adjustable axle housing shim between one end of the axle housing and a leaf spring. One end of the axle is moved by the adjustable axle housing shim to remove any skew in the axle and wheels.

A blockage aware zero skew clock routing method for calculating the distance, and therefore the delay, between two points takes into account any blockages along the path between the two points and therefore creates a more usable and realistic measure of delay and allows for minimization, or elimination, of clock skew in the system being designed using the method of the invention.

The invention discloses an ore pulp distributing and guiding device to solve the problem of unreasonable material distribution of conventional concentration tanks. The device is characterized in thata distributing and guiding device body is arranged below an outlet of a material distributing cylinder and comprises a static inner flow guide cover located at an upper position and a rotary outer flow guide cover located at a lower position, wherein the small end of the inner flow guide cover is connected with a central strut, and the large end of the inner flow guide cover is provided with a lower flange; and the outer flow guide cover is fixed on a rotating cage, the small end of the outer flow guide cover extends into the lower flange and is overlapped with the inner flow guide cover, thelarge end of the outer flow guide cover is positioned outside the rotating cage, and the diameter of the outer flow guide cover is greater than the diameter of a collecting hopper. The ore pulp distributing and guiding device changes flow direction and prevents coarse particle solids from directly sinking into the collecting hopper; the rotary outer flow guide cover is adopted, so secondary material distribution is achieved, and deflected settlement is eliminated; solids settled at the bottom of a pond is scraped and collected to the collecting hopper through a material scraping rake and are discharged out of the collecting hopper in time, so the collecting hopper is free of material accumulation and hardening which will leads to blockage of a discharging pipe; and discharging is smooth, overflow solid content and underflow concentration are stable, and a mud scraping rake works stably.

The invention relates to a novel self-potential riding wheel supporting device of a rotary cement kiln, which is formed by connecting a shifting bearing, a base, a rubber base, a radial elastic block and a sidewise elastic block. The novel self-potential riding wheel supporting device is characterized in that the shifting bearing consists of a movable support and a shaft arranged at the head of the movable support and linked with a plain redial bearing by two thrust articulated bearings; and sphere centers of the three bearings are coincided with the intersection point of a horizontal center line and a vertical center line of the shaft, and the inner cylindrical surface of the three bearings and the shaft form a hinged structure; both ends of the shaft are in square structures, one end of the shifting bearing is connected to the base by the square structures at the two ends of the shaft, and the other end is supported on the radical elastic block arranged on the rubber base. The invention has the advantages of simple structure, reliable use, convenient maintenance and long service life.

A semiconductor device includes transmission lines for conveying signals and transition detectors, each of which checks whether a transmission signal on each of the plurality of transmission lines is transited. If the signal is transited, its transition shape is detected. A signal mode determining unit determines signal transmission modes between adjacent transmission lines in response to output signals from the plurality of transition detectors. Delay units are coupled to the respective transmission lines for adjusting transmission delays of the transmission signals depending on corresponding output signal from the signal mode determining units.

The invention provides a method for eliminating error between different high-speed serial links through FIFO (First Input First Output). The method comprises the following steps of: S1, receiving synchronous data on each link and storing the synchronous data in FIFO which is correspondingly arranged in each link; S2, setting a Pop time point and simultaneously extracting the synchronous data from the corresponding FIFO on each link at the Pop time point; and S3, recovering the synchronous data which is extracted from the corresponding FIFO from each link into an original data frame. Compared with the prior art, the synchronous data transmitted on each link is stored in each FIFO which is correspondingly arranged, and data in each FIFO is simultaneously extracted out when the FIFO is read, so that Skew between every two links is eliminated, and furthermore, the data which is transmitted by the high-speed serial link is more easily recovered.

The present invention discloses a semiconductor memory device and a method for arranging signal lines thereof. The semiconductor memory device including a first memory cell array, an IO control circuit and a second memory cell array arranged between the first memory cell array and the IO control circuit, includes: first IO signal lines for transmitting data between the first memory cell array and the IO control circuit, wherein the first IO signal lines are connected to first data loading locations of the first memory cell array and extend in a straight line to the IO control circuit; and second IO signal lines for transmitting data between the second memory cell array and the IO control circuit, wherein the second IO signal lines are connected to first data loading locations of the second memory cell array and extend to the IO control circuit, wherein lengths of the first IO signal lines starting from the first data loading locations of the first memory cell array to the IO control circuit are identical to lengths of the second IO signal lines starting from the first data loading locations of the second memory cell array to the IO control circuit.

A data interface circuit includes a first latch corresponding to a first data signal, and suitable for outputting first data based on toggling of a data strobe signal; a second latch corresponding to a second data signal, and suitable for outputting second data based on toggling of the data strobe signal; and a skew control circuit suitable for delaying the first data signal by a predetermined time, applying the delayed first data signal to the first latch, controlling the delayed first data signal based on a result of comparing the first data signal and the second data signal, and applying the controlled delayed first data signal to the second latch.

The invention relates to the field of ground rail robots, in particular to a crawling ladder welding device based on a ground rail robot. The technical problem to be solved is to provide the crawling ladder welding device based on the ground rail robot. According to the technical scheme, the crawling ladder welding device based on the ground rail robot comprises a material placing assembly, a welding assembly and the like, and the material placing assembly is connected with the welding assembly. When the crawling ladder welding device is used, cutting is carried out on an L-shaped cross rod in advance, the two ends of a horizontal part of the L-shaped cross rod exceed the two ends of a vertical part respectively, then the two ends of the horizontal part are lapped on two vertical rods respectively, the the welding operation is carried out, and therefore the problem of poor stability caused by a small welding area is eradicated, the L-shaped transverse rod is perpendicular to the two vertical rods at the same time and then the welding operation is carried out, the phenomenon that the transverse rods are inclined after welding is eradicated, welding is sequentially carried out on the six transverse rods through a ground rail, meanwhile, automatic lubrication can be achieved, and lubricating oil is prevented from dripping into the device.

A hand-operated document processor includes a base including a perforated bed for receiving a document containing magnetic ink character data to be read and recognized. The base defines a chamber under the perforated bed. A manually operated moving magnetic ink character recognition (MICR) subsystem includes a MICR read head and is attached to the base such that movement of the subsystem causes the MICR read head to pass over the magnetic ink character data on the document. MICR reading and recognition logic receives the signal from the MICR read head. A document positioning and retentioning device connected to the base includes a manually-powered anti-skew device for creating a vacuum. The created vacuum is provided to the chamber under the perforated bed such that the vacuum, acting through the perforations, securely holds the document during the scanning operation.

The invention discloses a wave plate screw assembly. The wave plate screw assembly is mainly characterized in that a rod body of a locking part is provided with at least two propping parts; meanwhile, a broaching part is provided with clamping points; in the locking process, the broaching part can be stably and effectively driven to rotate by the locking part through clamping of the propping parts and the clamping points; the cutting capacity and effect of the broaching part are improved; when the propping parts are clamped onto the clamping points, the broaching part can be effectively corrected, and the condition that the broaching part is likely to skew when screwed in is eliminated.

A dynamic random access memory (DRAM) includes a delay lock loop (DLL), a clock tree, an off-chip driver (OCD), a phase detector (PD) and a filter. The DLL receives a reference clock and updates a delay line, and then outputs a calibrated clock via the clock tree; the PD receives the calibrated clock via the clock tree and detects a phase difference between the calibrated clock and the reference clock; and the filter activates the DLL to update the delay line according the phase difference, wherein when a READ command is received, the filter increases the number of activations for the DLL to update the delay line, thereby shortening the access time of the DRAM.

The invention provides a forme location fixture which is arranged on a platemaker, comprising a basal body and at least two group of positioning pin devices; each group is symmetrically arranged on the basal body; wherein, one group of positioning pin device which is adjacent to the edge of the basal body is a fixed positioning pin device and the other positioning pin devices are movable positioning pin devices; the invention also comprises a plurality group of clamping devices which are arranged on the basal body, and a position detection circuit board which is arranged on the basal body and corresponding to each positioning pin device; the position detection circuit board comprises an indicating device, a position detection circuit, an indicating on / off circuit, and a clamping on / off circuit; when misaligned location of the forme is detected by the position detection circuit, the indicating on / off circuit controls the indicating device to emit an instruct; when the aligned location of the forme is detected by the position detection circuit, the clamping on / off circuit controls the clamping device to clamp the forme. When the location fixture which is provided by the invention is applied to a computer direct platemaker, the location is exact, the inclined forme phenomenon is avoided, the consistency of the output forme on the platemaker is ensured, and the invention can be suitable for the forme location with different specifications.