45results about How to "Change in potential" patented technology

A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.

A MOS capacitor receiving a clock signal complementary to a sampling clock signal is provided at an input of a clocked inverter that is activated after sampling an input signal to perform level conversion. A charge pump operation of the MOS capacitor is performed in parallel with the activation of the clocked inverter. The power consumption of and the area occupied by a level conversion circuit converting a voltage amplitude of the input signal are reduced without deteriorating a high-speed operating characteristics.

A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.

When an idle period is started, a voltage of the control signal is changed from a value H to a value L. As a result, the analog amplifiers provided in the signal line driver circuit are switched from the normal state to the low-driving power state. At this time, the data signal lines are set to have a constant potential. A gate voltage is changed from Vgh to Vgl at the same time as when the control signal was changed from the value H to the value L. As a result, the gate of each TFT returns to the OFF state from the ON state. The control signal remains at the value L until the idle period is over. In other words, when the next driving period is started, the voltage of the control signal is changed from the value L to the value H. As a result, the analog amplifiers in the signal line driver circuit are switched back to the normal state from the low-driving power state.

The invention provides a semiconductor device capable of reducing wasteful power consumption. The semiconductor device of the invention does not require a refresh operation, and includes memory circuits for storing data, arranged in a matrix form, first signal lines for reading data from the memory circuits, second signal lines for transferring a signal that controls connection between the memory circuits and the first signal lines, a sense amplifier circuit for reading and determining data by detecting a potential change or a current change in the first signal lines, and a mitigating means for mitigating the potential change or the current change in the first signal lines during a period in which the sense amplifier circuit is being activated.

When there are a plurality of rows with the same display content, a scanning order calculating portion (23) provided in a display control circuit (200) determines addresses sequentially such that scanning signal lines corresponding to the rows are selected at the same time. A scanning order setting portion (24) controls an address output portion (26) such that the scanning signal lines are selected in such an order, and also controls digital image signals DV outputted by output frame memory (22). In this case, the number of changes in potential for video signal lines can be reduced by the number of rows selected at the same time, resulting in reduced power consumption for driving the video signal lines.

Provided are a plurality of circuit blocks each including: a first series circuit including a first rectifying element and a first switching element which are connected in series; a second series circuit including a second rectifying element and a second switching element which are connected in series; and a capacitor, wherein output terminals are connected to both ends of the first series circuit, both ends of the second series circuit, and both ends of the capacitor. Input terminals of the respective circuit blocks are connected in series. An AC power source is connected thereto via a choke, thereby solving the problem.

In an active matrix type liquid crystal display, during a non-display period such as the horizontal blanking interval or the vertical blanking interval wherein no pixel TFT is selected, the voltage of the opposing electrode is changed so that the power consumption is reduced with application of sufficient voltage to the liquid crystal and without increasing the amplitude of the display data. Also, a change alleviating voltage VM is applied during the change in the opposing electrode voltage to data lines for supplying display data to each of pixel TFTs during the display period, in order to prevent changes in the potential of the data lines caused by the change in the opposing electrode voltage and large reverse bias from being loaded to switches Hsw for outputting display data to the data lines.

A liquid crystal display device that is not influenced by a noise in obtaining positional information can be provided. The liquid crystal display device includes a first substrate provided with a pixel electrode and a common electrode with a first insulating film interposed therebetween. The pixel electrode and the common electrode partly overlap with each other. The liquid crystal display device further includes a second substrate provided with a pair of electrodes, a resin film covering the pair of electrodes, and a conductive film on the resin film. The pair of electrodes partly overlap with each other with a second insulating film interposed therebetween. The liquid crystal display device further includes a liquid crystal layer between the conductive film on the second substrate side and the pixel electrode and the common electrode on the first substrate side. A predetermined potential is supplied to the conductive film.

A video signal line driving circuit includes, for each output terminal TSj, a unit precharge circuit made of a capacitor Cpr and switches SWA1, SWA2, SWB1 and SWB2 for connecting the capacitor Cpr in parallel to a capacitive load of a liquid crystal panel. An OFF period in which first and second output buffers are electrically disconnected from the video signal line is provided between a P period in which a positive voltage is to be applied from the first output buffer in the video signal line driving circuit to the video signal lines (capacitive load) and an N period in which a negative voltage is to be applied from the second output buffer. A first and a second precharge period are set within this OFF period. In the first precharge period, the capacitor Cpr is connected in parallel to the capacitive load of the liquid crystal panel, and in the second precharge period, the capacitor Cpr is connected in parallel to the capacitive load with an orientation that is opposite to the orientation in the first precharge period.

To provide a display device with a novel structure that can achieve both thickness reduction and favorable display quality. In a structure of a display device including a liquid crystal layer between a pixel electrode and a counter electrode, a common electrode and an electrode of a capacitor in a touch sensor on the counter electrode side are formed integrally and supplied with a pulse signal. On the element substrate side, a signal to be supplied to a capacitor line that forms a capacitance with the pixel electrode is in conjunction with the pulse signal so as to cancel a change in an electric field applied to the liquid crystal layer. Such a structure can achieve a display device with a touch sensor function that can cancel a change in an electric field applied to a liquid crystal layer even when the electric field is changed by a pulse signal.

An electro-optical device includes a pixel circuit with a driving transistor element, a storage capacitor, and a capacitive element. The driving transistor element is electrically connected to a corresponding data line and a corresponding driving electrode. The storage capacitor is electrically connected to the driving transistor element and the driving electrode. The storage capacitor holds an image signal supplied through the corresponding data line as potential at the driving electrode. The capacitive element is electrically connected to the driving transistor element and the driving electrode. The capacitive element compensates for a change in the potential of the driving electrode when the driving transistor element is switched from a selection state to a non-selection state. The capacitive element is supplied with a correction signal that defines timing at which the potential of the capacitive element is controlled.

A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.

Switching TFTs are controlled to a conducting state and a switching TFT to a non-conducting state, to provide a potential according to a threshold voltage to a gate terminal of a driving TFT. Then, in at least one embodiment, with the TFT maintaining the conducting state, a potential of a data line Sj is changed from a reference potential Vpc to a data potential Vdata to place the TFT in a conducting state. At this time, a current Ia flows and thus the gate terminal potential of the TFT rises. The higher the mobility of the TFT, the larger the amount of change in gate terminal potential and the smaller the current flowing through an organic EL element upon light emission. By this, a current that is not affected by variations in the threshold voltage of the TFT nor by variations in the mobility of the TFT flows through the organic EL element. Thus, in a current-driven type display device, variations in both the threshold voltage and mobility of a drive element are compensated for.

A power supply to improve an EMI characteristic and an electronic device having the power supply. The power supply includes a power converter to convert an alternating current (AC) power applied from outside to a direct current (DC) power, a ground portion to supply a ground power to the power converter and a noise attenuator to reduce noise by blocking a harmonic current generated by a driving of the power converter from passing through the ground portion. Accordingly, the stable ground power can be supplied to the internal elements by avoiding the potential change of the ground power and the noise caused by the flow of the harmonic current can be reduced by shortening the harmonic current path. Therefore, the EMI characteristic can be improved.