144 results about "System Management Bus" patented technology

A network controller having a multiprotocol bus interface adapter coupled between a communication network and a computer bus, the adapter including a predictive time base generator; and a management bus controller adapted to monitor and manage preselected components coupled with one of the communication network and the computer bus. The management bus controller is adapted to employ an Alert Standard Format (ASF) specification protocol, a System Management Bus (SMBus) specification protocol, an Intelligent Platform Management Interface (IPMI) specification protocol, a Simple Network Management Protocol (SNMP), or a combination thereof. The network controller also includes a 10 / 100 / 1000BASE-T IEEE Std. 802.3-compliant transceiver and media access controller coupled with the communication network; a buffer memory coupled with the MAC, wherein the buffer memory includes one of a packet buffer memory, a frame buffer memory, a queue memory, and a combination thereof; and a transmit CPU and a receive CPU coupled with the multiprotocol bus interface adapter and the management bus controller. The network controller can be a single-chip VLSI device in an 0.18 micron CMOS VLSI implementation.

The invention provides a method for power management for a computer system. In one embodiment, the computer system comprises a system controller, a chipset, and a battery coupled to the chipset via a system management bus. First, a timer of the chipset is used to calculate an accumulated time value. When the accumulated time value exceeds a threshold value, the chipset is directed to send a system control interrupt to the system controller. After the system controller receives the system control interrupt, the system controller is triggered to detect a power level supplied by the battery via the system management bus.