86 results about "System level testing" patented technology

An automatic system level testing (ASLT) system for testing smart devices is disclosed. The system comprises a system controller operable to be coupled with a smart device in an enclosure, wherein the system controller comprises a memory comprising test logic and a processor. The system also comprises the enclosure, wherein the enclosure comprises a plurality of components, the plurality of components comprising: (i) a robotic arm comprising a stylus, wherein the stylus is operable to manipulate the smart device to simulate human interaction therewith; and (ii) a platform comprising a device holder, wherein the device holder is operable to receive a smart device inserted there into. The processor is configured to automatically control the smart device and the plurality of components in accordance with the test logic.

The invention is concerned with the testing of system level functionality involving several Protection. Control and Measurement (PCM) Intelligent Electronic Devices (IEDs) of a Substation Automation (SA) system for IEC 61850 compliant substations. An extensive testing of all conceivable control or protection functions / applications of an extended SA system comprising a large number of IEDs with a multitude of configurations is facilitated by simulating at least one of the IEDs in a testing device. Hence, only a limited number of IEDs are physically present as individual devices in a test environment, the behaviour of at least one further IED being simulated by a dedicated testing device with appropriate data processing means. The testing device sends network messages indicative of the behaviour of the simulated IED according to its communication and device configuration over a substation communication network to the physically present IED to be tested. The proper working of the configured IED functions, i.e. the expected correct action as triggered by the testing device, are then verified by analyzing the device's response over its analogue and digital outputs, as well as its response over the communication network. Preferably, the set-up for SA system testing is automatically detected and configured.

Protection, measurement and control IEDs in a substation compute if switches they control may be operated safely, according to interlocking rules or physical principles as well as the dynamic topology of the substation. The IEDs have access to the substation electrical topology, to real-time information generated by other IEDs, and to the rules for interlocking. A standardized Substation Configuration Description (SCD) of the substation for which a Substation Automation system is intended, and a standardized description of the implemented device functions or capabilities of an individual IED are utilized. The substation topology is available from SCD file, real time information about the position of switches and line voltage / current can be obtained via an appropriate protocol, and the interlocking rules are available in script form. These features apply both to simulated and real devices, and increase system testing possibilities by supporting an efficient configuration of a simulation.

A diagnostic and maintenance support system and process are provided for performing tests, collecting Built-In-Test (BIT) log data from systems, analyzing fault data, and recommending Shop Replaceable Units (SRU's). The system and process include uploading and reading a retrieved fault signature from a BIT log retrieved from a subject system under test. The retrieved fault signature is a serial word composed of a plurality of consecutive bits indicating either a pass or fail. Each bit is assigned to a specific SRU, system level test, or an event. The system and process further include a source code segment for performing a Discrete Fault Mask (DFM) algorithm, a Combinational Fault Mask (CFM) algorithm, and a source code segment for performing a Reserved Fault Mask (RFM) algorithm to identify a list of potentially problematic SRU's if matching bits are not found between the retrieved fault signature and the list of CFM serial words.

Methods and systems for testing an integrated circuit during an assembly process are described. The integrated circuit is received from inventory. The integrated circuit is placed in a socket on a first circuit board for system-level testing. The system-level testing is performed prior to placement and permanent attachment of the integrated circuit onto a second circuit board. Provided the integrated circuit passes the system-level testing, the placement and permanent attachment of the integrated circuit to the second circuit board is the next step following the system-level testing in the assembly process.