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SIP (system in package) chip testing platform and method

A chip test and chip technology, applied in the field of SIP chip test platform, can solve problems such as complex operation, failure to troubleshoot problems, and inability to fully guarantee performance, and achieve the effects of easy operation, low development cost, and simple structure

Active Publication Date: 2014-08-06
TECHTOTOP MICROELECTRONICS
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Problems solved by technology

However, this method requires the support of various sophisticated instruments and equipment, the operation is complicated, and it can only test its integrity and performance. It cannot fully guarantee the performance of the chip after it is packaged. When there is a problem with the packaged chip, it cannot be checked. The specific internal cause of the problem affects the test effect of the packaged chip

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  • SIP (system in package) chip testing platform and method
  • SIP (system in package) chip testing platform and method

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Embodiment Construction

[0018] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0019] The basic principle of the test method of this test platform is as follows: First, conduct a comprehensive evaluation of the combined work of the baseband and radio frequency chips before packaging, test the overall performance of a single baseband and radio frequency combination, and record the performance of the test in detail. The test performance is used as the performance test benchmark after SIP encapsulation. When testing the SIP-encapsulated chip, the tests performed using this test platform will record the corresponding performance parameters, and compare with the performance before...

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Abstract

The invention aims to provide an SIP (system in package) chip testing platform which at least comprises a power control module, an auxiliary testing base band, an auxiliary test radio frequency, a to-be-tested SIP chip and a communication control module. The to-be-tested SIP chip at least comprises a radio frequency and a base band, the power control module supplies power to the auxiliary testing base band, the auxiliary test radio frequency and the to-be-tested SIP chip, and the communication control module controls communication among the radio frequency and the base band of the to-be-tested SIP chip, the auxiliary testing base band and the auxiliary test radio frequency. By the aid of the platform, test problems about system-level tests on performance of the chip and checking of reasons causing reduction of the performance of the chip are solved, chip-level tests complicated in operation and high in cost can be omitted, and specific reasons causing the problems inside the SIP chip are determined via a simple mode; furthermore, the testing platform has the advantages of simple structure, easiness in operation, low development cost, flexibility in operation and the like.

Description

technical field [0001] The invention relates to a testing platform and method of a SIP chip, in particular to a testing platform and a testing method of a SIP chip in which radio frequency and baseband are packaged in the same chip. Background technique [0002] Aiming at the problem of SIP chip testing, there are some methods to test at present, such as mounting semiconductor chips on the substrate, forming internal wiring on the substrate, using external terminals on the semiconductor, etc. to test the quality of the bare chip. However, this method requires the support of various sophisticated instruments and equipment, the operation is complicated, and it can only test its integrity and performance. It cannot fully guarantee the performance of the chip after it is packaged. When there is a problem with the packaged chip, it cannot be checked. The specific internal cause of the problem affects the test effect of the packaged chip. [0003] Therefore, need a kind of test p...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28
Inventor 陈永耀吴钊锋
Owner TECHTOTOP MICROELECTRONICS
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