37 results about "Synchronous oscillator" patented technology

A data emission / reception device by inductive coupling includes an inductive antenna circuit in which an antenna signal appears, a mechanism configured to for extracting a first periodic signal from the antenna signal, a synchronous oscillator receiving the first periodic signal and supplying a second periodic signal, and an active load modulation circuit configured to apply bursts of the second periodic signal to the antenna circuit. The device is configured to place the oscillator in the synchronous oscillation mode before each application of a burst of the second periodic signal to the antenna circuit, then place the oscillator in the free oscillation mode.

A radio frequency device has an antenna for capturing an incoming signal for processing by the device or for radiating an outgoing signal from the device and a signal processor having one or more synchronous oscillators responsive to an input signal for providing an amplified output signal without using much power. An application is a radio frequency (RF) transponder (tag) for receiving an RF signal from an interrogator includes a tag antenna for receiving the RF signal from the interrogator and a receiver section connected to the tag antenna wherein the receiver consumes a significantly lower amount of power than conventional receiver technologies by using one or more synchronous oscillators.

A method for sending data by inductive coupling includes: extracting an antenna signal from an antenna circuit, extracting from the antenna signal a first periodic signal, producing a second periodic signal by way of a synchronous oscillator, placing the oscillator in a free oscillation mode and applying to the antenna circuit the second periodic signal, modifying the impedance of the antenna circuit, restoring the amplitude of the antenna signal, then resynchronizing the oscillator on the first periodic signal.

A controller for controlling at least two power circuits comprises a synchronous oscillator and a multi-phase PWM controller. The synchronous oscillator receives a timing signal for generating a synchronous control signal in which the timing signal is synchronous to a display signal. The multi-phase PWM controller receives the synchronous control signal for generating at least two PWM signals. The at least two PWM signals are coupled to the at least two power circuits for driving the at least two power circuits respectively. The at least two PWM signals are synchronous to the timing signal and with a phase shift between the at least two PWM signals.

An apparatus and method for receiving a quick paging message in a mobile station wherein a controller for synchronizing with a second clock in a predetermined time slot and transmitting a command for obtaining a synchronization at a frequency of receiving the quick paging message where the MS selects a clock having a first period as an operation clock under the second mode and under the first mode, selects a clock having a second period earlier than the first period; a dual phase-locked loop operating in response to the clock selected by the controller, for synchronizing with frequency in response to the command from the controller; a oscillator for oscillating at the synchronized frequency with the dual phase-locked loop; and a radio frequency part for receiving the quick paging message over a forward quick paging channel synchronously with the oscillating frequencies.

Systems and methods which provide an oscillator circuit outputting non-overlapping trigger signals throughout a range of operating voltages using a reset-set (RS) flip-flop type circuit configuration are shown. Embodiments utilize output driver buffers internal to the RS flip-flop circuit configuration to provide oscillator feedback delay. Feedback control circuitry may be implemented to ensure that the delay associated with any one driver buffer does not solely provide the feedback delay. Embodiments further implement input delay circuitry adapted to maintain a relatively constant reset and set input feedback delay ratio throughout a large range of operating conditions.

A controller for controlling at least two power circuits comprises a synchronous oscillator and a multi-phase PWM controller. The synchronous oscillator receives a timing signal for generating a synchronous control signal in which the timing signal is synchronous to a display signal. The multi-phase PWM controller receives the synchronous control signal for generating at least two PWM signals. The at least two PWM signals are coupled to the at least two power circuits for driving the at least two power circuits respectively. The at least two PWM signals are synchronous to the timing signal and with a phase shift between the at least two PWM signals.

A control circuit generates a driving signal for driving a light-emitting element. An external synchronization oscillator receives a synchronization clock signal from an external circuit, and generates an external synchronization cyclic signal synchronously with the clock signal. An internal oscillator generates an internal cyclic signal having a predetermined frequency asynchronously with the synchronization clock signal. When the frequency of the external synchronization cyclic signal is within a predetermined range, the driving signal generating unit generates the driving signal based upon the external synchronization cyclic signal. When the frequency of the external synchronization cyclic signal deviates from the predetermined range, the driving signal generating unit generates the driving signal based upon the internal cyclic signal.

A modification of the synchronous oscillator is described, having regenerative positive feedback. The circuit includes an amplifier, a high-Q tank circuit, and a conventional synchronous oscillator feedback network. An additional feedback path provides a negative impedance conversion effect.

The invention relates to a synchronous oscillator circuit which forces synchronization according to an external input synchronous signal. The invention discloses the synchronous oscillator circuit for solving the problems associated with frequency, such as electromagnetic interference, switch noise of the circuit, and the problem of improving the stability of clock signal of the circuit. The technical scheme is as follows: the synchronous oscillator circuit comprises a first comparator, a second comparator, a third comparator, a synchronous control circuit, an SR latch, an NMOS (N-channel Metal Oxide Semiconductor) tube, a resistor and a capacitor. The synchronous oscillator circuit in a work mode of controlling inner frequency of the circuit by the external period signal has the characteristic of high stability, and can solve the problems associated with frequency, such as the electromagnetic interference and the switch noise of the circuit,. The circuit has the characteristics of simple structure, easiness in transplanting and adjustability of external frequency, and can be widely applied to various functional circuits, and in particular to a switch power supply to reduce interference to the circuit when the switch power supply works at certain frequency.

The invention provides an oscillator circuit with an external synchronization function, which belongs to the technical field of electronic circuits. An external resistor is added in the oscillator circuit, and the size of the external resistor is adjusted to adjust the own oscillator frequency. Another synchronous circuit is added. Through a synchronization control signal SYNC, forced synchronization of the oscillator frequency is realized, and a stable and reliable clock signal CLK is acquired. A constant current source is used to discharge an oscillator capacitor, so that the discharge time, namely the high level time of the clock signal CLK, is controllable. The problem that the can not respond, which is caused by too short high level time of the clock signal CLK, is solved. According to invention, the oscillator circuit has the advantages of adjustable oscillation frequency, external synchronization and high stability, and can effectively suppress intermodulation interference, electromagnetic interference and other problems in the circuit.

Timepiece movement or watch including one isochronous oscillator mechanism, including only a first sprung balance oscillator including a first balance spring attached to a fixed structure at a first stud and to a first mobile component pivoting about a first axis, and a second sprung balance oscillator including a second balance spring fixed to a second mobile component, coupled to each other by mechanical connection via this second elastic return means attached to the first mobile component, this second balance spring being attached, to a felloe or an arm of the first mobile component at a second stud, and to this second mobile component which pivots about a second axis, and the maintenance of the oscillations is effected on only one of first mobile component or second mobile component.

Disclosed herein is a synchronous oscillator including at least one injection circuit having an injection signal input terminal, an internal clock signal input terminal, and a clock output terminal, and at least one delay circuit cascaded to the injection circuit.

An IC includes an internal circuit that switches between on-state and off-state in response to an external signal and also includes an oscillator circuit that is externally synchronized. The IC further includes a state holding circuit that, when pulses for synchronizing the oscillator circuit are inputted to a standby pulse input terminal, applies, to the internal and oscillator circuits, as an operation signal, a voltage obtained by rectifying pulses outputted from a comparator, and, when a constant voltage for non-operation is applied to the standby pulse input terminal for a given time period, applies, to the internal and oscillator circuits, as a non-operation signal, a constant voltage outputted from the comparator.

A frequency measuring and control apparatus includes a plurality of synchronized oscillators integrated in parallel into one programmable logic device.

The invention discloses a bidirectional frequency synchronous oscillator circuit. The circuit comprises an oscillator main body module, a synchronous clock signal generation module, an external clocksignal detection module and an internal and external clock signal mutual interference prevention module; the oscillator main body module is connected with an external resistor to control triangular wave signals generated by periodic charging and discharging of an external capacitor, and the oscillator main body module internally comprises a charging and discharging circuit of the external capacitor and related control circuits; when no clock signal exists outside, the synchronous clock signal generation module outputs the clock signal generated by the oscillator main body module, and the clocksignal can be used as a clock signal of other power supply systems; the external clock signal detection module is used for detecting whether an external clock signal exists or not, and controlling the oscillator main body module to synchronize to the external clock signal when the external clock signal is detected; the internal and external clock signal mutual interference prevention module is used for avoiding mutual interference between an external clock signal and an internally generated clock signal, so the external clock signal and the internally generated clock signal cannot appear at the same time, and logic errors are avoided.

Systems and methods which provide an oscillator circuit outputting non-overlapping trigger signals throughout a range of operating voltages using a reset-set (RS) flip-flop type circuit configuration are shown. Embodiments utilize output driver buffers internal to the RS flip-flop circuit configuration to provide oscillator feedback delay. Feedback control circuitry may be implemented to ensure that the delay associated with any one driver buffer does not solely provide the feedback delay. Embodiments further implement input delay circuitry adapted to maintain a relatively constant reset and set input feedback delay ratio throughout a large range of operating conditions.

The device resonant comprises a plurality of synchronized oscillators. Each oscillator comprises a resonator which comprises detection means providing detection signals representative of oscillation of the resonator to a feedback loop connected to an excitation input of the resonator. The detection signals control the conductivity of the feedback loop of the oscillator. The excitation inputs of all the resonators are connected to a common point which constitutes the output of the resonant device. A capacitive load is connected between said common point and a reference voltage.

A transition state acquisition device includes an oscillator that includes a tapped delay line and a combination circuit provided on a signal path from one end to the other end of the tapped delay line, and oscillates based on a first signal, and a latch that captures and holds an output signal of the tapped delay line in synchronization with a second signal. The oscillator starts a transition of a state of the tapped delay line based on the first signal. An interval between timings at which the latch captures the output signals of the tapped delay line is shorter than a time during which the state transition of the tapped delay line makes one round.

Disclosed herein is a synchronous oscillator including at least one injection circuit having an injection signal input terminal, an internal clock signal input terminal, and a clock output terminal, and at least one delay circuit cascaded to the injection circuit.

The invention provides a display driving module, a control method thereof and a display driving system. The display driving module executes a control method and comprises an adjustable frequency oscillator and a correction unit, and the correction unit outputs frequency correction information to enable the adjustable frequency oscillator to generate a gray scale clock signal with the frequency within a target frequency range. The pulse width modulation unit generates a pulse width control signal according to the gray scale clock signal and driving information, and a driving output unit receives the pulse width control signal and outputs a driving signal according to the pulse width control signal; a display driving system comprises more than two driving modules, and the two driving modulesrespectively comprise non-synchronous oscillators with different frequencies, so that the two gray-scale clock signals cannot be switched synchronously, high-frequency noise of the two driving signals is prevented from being generated at the same time, EMI (electro-magnetic interference) frequency spectrums of the driving signals can be dispersed. And the glitch noise of the frequency spectrum ofthe EMI at a specific frequency is reduced.

A molecular fluorine laser includes a discharge chamber filled with a gas mixture including molecular fluorine and a buffer gas and not including a laser active rare gas, multiple electrodes within the discharge chamber defining a discharge region therebetween connected to a pulsed discharge circuit for applying discharge pulses to the electrodes for energizing the gas mixture, and a resonator including the discharge chamber for generating an oscillator laser beam at a wavelength around 157 nm and a bandwidth of less than 0.6 pm. The laser further includes a power amplifier for increasing the energy of the attenuated oscillator laser beam to a second predetermined energy for lithographic processing, a line-narrowing unit for reducing the bandwidth, a low intensity suppressor module to suppress the weaker lines of the F2-laser, and a synchronization unit to synchronize the oscillator and amplifier.

The invention relates to a transmitting device of a wireless power supply system, the wireless power supply system and a wireless illuminating system. A power supply unit converts external alternatingcurrent into direct current to supply power for a control unit and a transmitting unit. The control unit sends an enabling signal and a PWM voltage regulating signal to the central control circuit. When the enabling signal is at a high level, the central control circuit controls a synchronous oscillator to vibrate. An IGBT driving circuit drives the IGBT power tube for power output. A resonance rings vibrate, so that the electric signals are converted into wireless magnetic signals for output. Wiredly transmitted electric energy can be converted into the wirelessly transmitted magnetic signalto supply electric energy to electricity consumption equipment. The convenience and the safety of the power supply mode are improved.

A frequency measuring and control apparatus includes a plurality of synchronized oscillators integrated in parallel into one programmable logic device.

On vehicles provided with a single reception antenna or with several adjacent reception antennas (A3, A4) coupled to the go-and-return lines of a track conductor (L), the phase angle of the reception voltage is retained when the reception level falls below a particular reception level (SW1). If the level (SW2) of the reception voltage rises again, the actual phase position of the reception voltage (UA3) can be compared with the retained reception voltage. When the phases of the reception voltages to be compared are in opposition, one concludes that the vehicle is passing over a track conductor crossing (K). When the phases of the reception voltages to be compared are the same, this indicates a passing transmission disturbance. The phase angle of the comparison voltage is preferably retained by a flywheel oscillator. The difference in time between actual reception voltage (UA3) and comparison voltage is preferably determined by evaluating the peak values of both voltages.

The invention discloses an oscillator arrangement and method for synchronizing an oscillator. The oscillator arrangement having an oscillator configured to generate an oscillation signal having two half-cycles, an input configured to receive a synchronization signal including synchronization triggers, a synchronizer configured to reject a synchronization trigger received during a first part of a half-cycle and to synchronize the oscillator to a synchronization trigger received during a second part of the half-cycle, and a controller configured to prolong the second part of the half-cycle in response to receiving a synchronization trigger during the first part of the half-cycle.