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91 results about "Synchronous Data Flow" patented technology

Synchronous Dataflow is a restriction of Kahn process networks where nodes produce and consume a fixed number of data items per firing. This allows static scheduling.

Using time-stamped event entries to facilitate synchronizing data streams

An embodiment of a system to synchronize data streams is described. During operation, the system receives a first data stream having a first data type and performs a sequence of operations on at least a portion of the first data stream. Next, the system stores metadata associated with the first data stream one or more times during the sequence of operations. Metadata can include a time stamp, data-stream information associated with the portion of the first data stream, and event information associated with the occurrence of one or more events during the sequence of operations. Moreover, the system provides a notification based on the stored metadata, the notification to facilitate synchronizing the first data stream with a second data stream having a second data type.
Owner:APPLE INC

Method and system for efficient framing on addressed buses

A framing mechanism may be provided that enables passing of messages over an addressed bus. This creates a form of information hiding, which passes information by converting an addressed bus interface to a message-based bus interface. Address-based information in a transaction may be replaced with additional information that specifies framing details comprising, for example, a check pattern and length information. The check pattern provides a mechanism for determining whether frame information may be valid. An end device may utilize this length information to determine an actual length of an incoming frame. The combination of the check pattern and the length information may provide a pattern for resynchronizing a data stream when errors are detected. The framing mechanism may operate over existing addressed buses without requiring host side controller hardware modifications and additional host side software driver may be utilized to add the framing information.
Owner:AVAGO TECH INT SALES PTE LTD

Method for processing synchronous priority bursty flow in data center network

The invention provides a method for processing synchronous priority bursty flow in a data center network. The method comprises the steps that the order of distribution priorities of the data flow is determined according to the magnitude of values of urgency factors pri, the urgency factor pri having the minimal value in a default mode has the lowest priority; an exchanger calculates the speed reduction probability pj for M strips of priority synchronous data flow with request window values larger than expectation window values in the same link; MXpj strips of data flow are randomly selected according to the M strips of data flow, urgency factors prj of the MXpj strips of data flow are regulated into minimal values, sending speed of the MXpj strips of data flow is reduced, and MX(1-pj) strips of data flow of the M strips of data flow are smoothly transmitted under the wire. The method resolves the problem of the synchronous priority bursty flow in the data center network, avoids network congestion, and meanwhile reduces the deadline missing rate.
Owner:广西优耐信息技术有限公司

Method and apparatus for synchronizing multimedia data stream

A method and an apparatus for synchronizing a data stream are disclosed. The method includes: decoding the data stream to generate a decoded data stream and program clock references; generating a local clock reference; generating a simulated clock reference according to the program clock references and the local clock reference; comparing the local clock reference with the simulated clock reference to generate a comparison result; adjusting a processing timing of the decoded data stream according to the comparison result; and processing the decoded data stream according to the processing timing.
Owner:REALTEK SEMICON CORP

Fast classification method, method and device for EEG signals based on FPGA

The invention discloses a fast classification method of EEG signals based on FPGA, a realization method and a device thereof. The hard logic of a CNN network structure model suitable for the classification of EEG signals is constructed on FPGA, and the convolution operation is converted into matrix multiplication. The IP cores of each layer in the CNN network structure model are established, and the IP cores of each layer in the CNN network structure model are connected by using the synchronous data flow method, and AXI4-Streaming register chip is inserted between the adjacent IP cores; the EEG training data is received, the floating-point data is converted to a fixed-point number with a preset number of bits, training the CNN network structure model, adjusting the CNN network structure model weight value until the highest classification accuracy model is obtained, and the trained model parameters are stored in DDR memory, so as to obtain FPGA which can realize the fast classificationof EEG signals, and the fast classification of EEG signals is carried out by using the CNN network structure model.
Owner:SHANDONG NORMAL UNIV

Clock synchronization of data streams

A system synchronizes data flow between a first device and a second device. The system includes a data link that connects two or more devices that are capable of sending and receiving data through a bus. A capture device senses and transfer information through the bus. A ring buffer temporarily stores data transmitted through the bus. A read controller copies or reconstructs data in a length that is different from the length of the data received. A monitor detects underflow or overflow conditions into or out of the ring buffer and compensates for clock drift.
Owner:BLACKBERRY LTD

Fast ergodic synchronous data flow system node parameter processing method based on graphs

The invention discloses a fast ergodic synchronous data flow (SDF) system node parameter processing method based on graphs. The fast ergodic synchronous data flow system node parameter processing method includes that an SDF graph is built for a real-time system, communication parameters of nodes connected at two ends on the side are marked at the two ends of each side in the graph, a node needed to be temporarily stored in the SDF graph stacking and storing ergodic process is built, any one node in the SDF is selected and operation parameters of the selected node are initialized, scanning is started, whether rings exist in the graph can be judged when each node is scanned, operation parameter consistency judgment is performed on yes judgment, otherwise, the operation parameters of the node are determined on the basis of communication parameters of the node, and the operation parameters of the scanned nodes in the graph are subjected to overall normalized adjustment. The fast ergodic synchronous data flow system node parameter processing method is few in processing steps, small in calculating amount, high in efficiency and accurate in calculating result, has the universalizaion advantage of being capable of processing parameters in different attributes, and improves speed and efficiency of computers for processing real-time SDF system node operation parameters.
Owner:BEIHANG UNIV

Synthesis Path For Transforming Concurrent Programs Into Hardware Deployable on FPGA-Based Cloud Infrastructures

Exploiting FPGAs for acceleration may be performed by transforming concurrent programs. One example mode of operation may provide one or more of creating synchronous hardware accelerators from concurrent asynchronous programs at software level, by obtaining input as software instructions describing concurrent behavior via a model of communicating sequential processes (CSP) of message exchange between concurrent processes performed via channels, mapping, on a computing device, each of the concurrent processes to synchronous dataflow primitives, comprising at least one of join, fork, merge, steer, variable, and arbiter, producing a clocked digital logic description for upload to one or more field programmable gate array (FPGA) devices, performing primitive remapping of the output design for throughput, clock rate and resource usage via retiming, and creating an annotated graph of the input software description for debugging of concurrent code for the field FPGA devices.
Owner:RECONFIGURE IO LTD

Credible sorting method of synchronous data flow procedures based on formal verification

The invention discloses a credible sorting method of synchronous data flow procedures based on formal verification. The credible sorting method comprises a Lustre parallel program and a serial C program obtained after sorting of the Lustre parallel program. For any two Lustre programs meeting the requirement for topological sorting, execution semantic equivalence of a Lustre program before topological sorting and a Lustre program after topological sorting is proved, and a C program after sorting and the Lustre program before sorting are equivalent in semantic execution. The credible sorting method of synchronous data flow procedures based on formal verification is developed and achieved based on a formalized language and with a 'vertex topological sorting algorithm with the in-degree as zero' as the theoretical basis. By means of the provement that any two programs meeting the topological sorting property are equivalent in serial semantic execution, during formal verification, all the situations in the process that a parallel language is converted into a serial language, each situation is proved, the program after sorting meets the topological sorting property, so that correctness of a scheme is ensured, and safety and reliability of a whole software system are improved.
Owner:CHINA TECHENERGY +1
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