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175 results about "Cobalt silicide" patented technology

Process for forming cobalt and cobalt silicide materials in tungsten contact applications

Embodiments of the invention described herein generally provide methods for forming cobalt silicide layers and metallic cobalt layers by using various deposition processes and annealing processes. In one embodiment, a method for forming a metallic silicide containing material on a substrate is provided which includes forming a metallic silicide material over a silicon-containing surface during a vapor deposition process by sequentially depositing a plurality of metallic silicide layers and silyl layers on the substrate, depositing a metallic capping layer over the metallic silicide material, heating the substrate during an annealing process, and depositing a metallic contact material over the barrier material. In one example, the metallic silicide layers and the metallic capping layer both contain cobalt. The cobalt silicide material may contain a silicon / cobalt atomic ratio of about 1.9 or greater, such as greater than about 2.0, or about 2.2 or greater.
Owner:APPLIED MATERIALS INC

Structure and method for enhanced uni-directional diffusion of cobalt silicide

InactiveUS20060057844A1Improves suicide processReducing Si consumptionSemiconductor/solid-state device detailsSolid-state devicesSelf limitingSilicon alloy
The present invention provides a method for enhancing uni-directional diffusion of a metal during silicidation by using a metal-containing silicon alloy in conjunction with a first anneal in which two distinct thermal cycles are performed. The first thermal cycle of the first anneal is performed at a temperature that is capable of enhancing the uni-directional diffusion of metal, e.g., Co and / or Ni, into a Si-containing layer. The first thermal cycle causes an amorphous metal-containing silicide to form. The second thermal cycle is performed at a temperature that converts the amorphous metal-containing silicide into a crystallized metal rich silicide that is substantially non-etchable as compared to the metal-containing silicon alloy layer or a pure metal-containing layer. Following the first anneal, a selective etch is performed to remove any unreacted metal-containing alloy layer from the structure. A second anneal is performed to convert the metal rich silicide phase formed by the two thermal cycles of the first anneal into a metal silicide phase that is in its lowest resistance phase. A metal silicide is provided whose thickness is self-limiting.
Owner:GLOBALFOUNDRIES INC

Semiconductor device and its making method

The invention discloses a metal oxide semi-conductor device, which comprises a semi-conductor underlayer, a grid structure formed on the surface of the underlayer, and the two sides of which have side wall isolators, a source electrode area and a drain electrode area positioned on the two sides of the side wall isolators on the underlayer, a first metal silicide positioned on the source electrode area and the drain electrode area, and a second silicide positioned on the grid structure. The manufacturing method of semi-conductor devices of the invention forms respectively the first metal silicide containing the first and the second metal, and forms the second silicide containing the second metal. The invention combines the advantages of both the cobalt silicide techniques and the nickel silicide techniques, and applies well the nickel silicide techniques to the following technique nodes below 65nm. The invention reduces the risk of forming spriking in the source / drain area, when assuring the formation of metal contact layer of high reliability on the surface of the grid by using nickel silicide.
Owner:SEMICON MFG INT (SHANGHAI) CORP +1

Semiconductor device and method of manufacturing the same

A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.
Owner:RENESAS ELECTRONICS CORP

Bipolar/bicmos semiconductor device

An N type buried layer is buried in a P type silicon substrate. An N type epitaxial layer is formed on this buried layer. A P type intrinsic base region and an extrinsic base region are formed on the surface of the epitaxial layer. An N type emitter region is formed in the intrinsic base region. An emitter electrode is formed to contact the emitter region. A collector plug region is formed in an area separated from the extrinsic base region through a filed insulating film. A cobalt silicide film is formed on the extrinsic base region to surround the emitter electrode. An extrinsic base contact hole is formed at only one side of the emitter electrode. In the semiconductor device, the base resistance Rb and the collector-base capacity Ccb are reduced to make the maximum oscillation frequency fmax sufficiently large.
Owner:RENESAS ELECTRONICS CORP
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