180 results about "Active storage" patented technology

Online marketing platforms are disclosed that harness user generated content to encourage the viral sharing and tracking of online marketing campaigns. One embodiment includes a campaign hosting system including a database connected to a network, a campaign creation device connected to the network and a plurality of user devices connected to the network. In addition, the campaign creation device is configured to provide campaign information to the campaign hosting system via the network, the campaign hosting system is configured to automatically create an online campaign that is customized according to the campaign information and to store the campaign as one of a plurality of online campaigns in the database, at least one of the user devices is configured to provide profile information to the campaign hosting system via the network, the campaign hosting system is configured to automatically create a user profile using the profile information and to store the user profile as one of a plurality of user profiles in the database, each user device is configured to engage with the online campaign by communicating with the campaign hosting system via the network and each user device is configured to access the user profile by communicating with the campaign hosting system via the network.

Provided is a method and system for distributing a test recipe to a tester for conducting a test to determine if a device under test operates as designed. The method includes storing an active test recipe in an active memory in local communication with the tester, and initiating the test of the device under test to be performed by the tester according to a parameter included in the active test recipe stored in the active memory. A second parameter included in a second test recipe is received by the tester while conducting the test of the device under test according to the parameter included in the active test recipe. The method further includes storing the second parameter in a buffer memory in local communication with the active memory, and initiating a transfer of the second parameter from the buffer memory to the active memory. After initiation of the transfer of the second parameter to the active memory, a subsequent test to be performed by the tester according to the second parameter included in the second test recipe is initiated.

A method for displaying graphical objects is provided. In one embodiment, the method includes accessing a data structure including a plurality of sequential data objects and the location of associated graphical data stored in a non-volatile storage device. Further, the method may include rendering a first graphical object associated with a first data object of the data structure in a viewport of a device, including loading the graphical data for the first data object from the non-volatile storage into an active memory. The method may also include rendering a second graphical object in the viewport based on the location of the second data object with respect to the first data object within the data structure. In one embodiment, graphical data for data objects is loaded into the active memory on an as-needed basis. Various devices, machine-readable media, and other methods for displaying graphical objects are also provided.

A method for linking online computer activity with non-online consumer activity by creating a unique identifier for each consumer; storing online and non-online consumer activity in a database indexed by the unique identifier; and modifying online or non-online consumer offerings based on processing the stored online and non-online consumer activity.

Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.

Sophisticated memory systems and intelligent machines may be constructed by creating an active memory system with a hierarchical architecture. Specifically, a system may comprise a plurality of individual cortical processing units arranged into a hierarchical structure. Each individual cortical processing unit receives a sequence of patterns as input. Each cortical processing unit processes the received input sequence of patterns using a memory containing previously encountered sequences with structure and outputs another pattern. As several input sequences are processed by a cortical processing unit, it will therefore generate a sequence of patterns on its output. The sequence of patterns on its output may be passed as an input to one or more cortical processing units in next higher layer of the hierarchy. A lowest layer of cortical processing units may receive sensory input from the outside world. The sensory input also comprises a sequence of patterns.

A memory system includes an active storage circuit and at least one base storage circuit. The at least one base storage circuit is coupled to the active storage circuit though at least one pass gate, at least one driver and a bit line. The at least one pass gate and the at least one driver have a device size substantially similar to a device size of each one of the devices in the active storage circuit and the at least one base storage circuit. A method of swapping data between two storage circuits is also described.

A computer for implementing a method for conditionally capturing hardware scan dump data to minimize the reboot recovery time employs a service processor operable to detect a failure of another hardware component of the computer. Upon detection, the service processor will conditionally capture hardware scan dump data. The first condition for capturing hardware scan dump data is the service processor being activated into an active storing mode of operation labeled “Always”. The second condition for capturing hardware scan dump data is the service processor being activated to a reactive storing mode of operation labeled “As Needed” and the error causing the operational failure being a type of error where hardware scan dump data is needed or desired by a system engineer in correcting the operational failure. By conditionally capturing hardware scan dump data, the amount of data being processed over multiple failures of the computer is minimized.

Crash recovery of a computing system in the context in which the computing system includes a volatile memory which has contents lost due to the crash, an intermediate non-volatile memory that (together with the volatile memory) contributes to the active memory of the computing system, and non-volatile storage. The recovery occurs by identifying pages that were in the volatile memory at the time of the crash. For each of these pages, the recovery determines whether to recover the page into the volatile memory from either the intermediate non-volatile memory or the storage, and then performs the recovery. In embodiments in which access speeds for the intermediate non-volatile memory may be much faster than for the storage, and in which much of the pages to be recovered are recovered from the intermediate non-volatile memory, the recovery time may be reduced.

A method and apparatus to modify control devices residing on a Fieldbus communications network, without interrupting the operation of the control devices. The control device updating may further be controlled and monitored by a remotely located host that also communicates on the Fieldbus network. The control device may comprise at least two distinct memory areas, wherein at least one memory area must be active, and at least one memory area must be inactive. Active memory areas provide the control device microprocessor operating system with executable instructions or data. The host downloads new executable instructions or data to inactive memory areas, with associated data entry points, during unscheduled communications periods wherein data input / output is not being performed between the control device and the host or another control device. Upon a full data transfer and proper verification of the new data, the host may issue an activation command that causes a selector device to activate the previously inactive memory area by directing the microprocessor to the entry points of the newly downloaded executable instructions or data. The memory activation must occur while the microprocessor is not performing application execution, application input / output, or application communications. By timing the memory activation in this manner, the microprocessor may be redirected to the newly downloaded executable instructions or data without microprocessor interruption.

The configuration of a cache memory can be changed while minimizing the influence over input-output performance with a host system on the active storage system.A data transfer control unit transfers data via a cache memory by a write-after method; and as triggered by an event where an amount of input to and output from an object area in the cache memory falls below a certain value, the data transfer control unit switches from the write-after method to a write-through method and then transfers data via the cache memory. Subsequently, as triggered by an event where there is no longer any input to and output from the object area in the cache memory, a processor changes the configuration of the cache memory relating to the object area.