38results about How to "Reduce write latency" patented technology

Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method of managing memory includes determining a temperature associated with the memory and determining a level of write queue utilization associated with the memory. A write operation may be performed based on the level of write queue utilization and the temperature.

A first method for efficient memory usage includes (1) determining whether data retrieved from a first storage device is characterized as data that is primarily read; and (2) if data retrieved from the first storage device is characterized as data that is primarily read (a) writing the retrieved data in a temporary storage device with short write latency; and (b) writing the retrieved data in a high-density memory. Numerous other aspects are provided.

The invention relates to the technical field of computer data storage, in particular to a method, device and system for writing data pairs in LevelDB databases. The method provided herein comprises: configuring multiple LevelDB databases corresponding to multiple message queues; writing data pairs into one message queue; writing the data pairs of the message queue into the LevelDB database corresponding to the message queue, wherein before configuring the multiple databases corresponding to the multiple message queues, steps also are included which include: creating multiple catalogues, and configuring multiple catalogues corresponding to the multiple LevelDB databases, and wherein writing the data pairs into one message queue includes: allocating the data pairs among the multiple message queues through Hash algorithm, and determining the message queue which the data pairs are to be written in. The problem that writing performance of LevelDB databases under high stress is low is solved, and the writing performance of LevelDB databases is improved.

The invention discloses a writing method for a resistive random access memory based on a crosspoint array, belonging to the field of information storage. The method of the invention increases effective voltage and reduces write delays by dynamically selecting the shortest voltage drop path; one regional division manner is employed to reduce differences among write delays in each area, so write delays in each area are reduced, and unit-level parallelism is guaranteed at the same time; the mapping between physical addresses and unit locations is established by employing an addressing mode, so write delays increase with the physical addresses, which facilitates optimization of address mapping, memory allocation and compilation; a parallel addressing circuit system is provided to speed up theaddressing process; and SET and RESET processes are overlapped for units in different rows and columns in virtue of a specific voltage bias mode, and row-level parallelism in the crosspoint array is developed. The method of the invention can reduce the write delays of the resistive random access memory, increase write bandwidth, and decrease the power consumption of writing.

Static random access memory (SRAM) bit cells employing asymmetric width read and write word lines (WWL) for reduced memory write latency and improved memory write access performance, and related fabrication methods are disclosed. In exemplary aspects, the SRAM bit cell employs an increased width write word line based on a circuit cell layout area savings achieved by employing a reduced width read word line. Increasing the width of the write word line can reduce the resistance of the write word line and decrease memory write latency to the SRAM bit cell as a result. In certain exemplary aspects, the metal line pitch and minimum distance between metal lines of the SRAM bit cell can be maintained for maintaining fabrication compatibility with existing fabrication processes with decreasing the resistance of the write word line of the SRAM bit cell.

The embodiment of the present invention discloses a method and device for reducing write latency in a solid-state hard disk under GC. The method includes separately counting the number of different data blocks, and the different data blocks include GC source blocks, GC destination blocks, and free blocks provided for LKM ; Perceive the write pressure and GC efficiency of HOST according to the number of different data blocks, and calculate the arbitration value; send the arbitration value to LKM, and LKM allocates data frame resources for GC writing according to the arbitration value. The invention senses the writing pressure of the HOST, measures the writing pressure and GC efficiency, and allocates appropriate data frame resources for the GC based on this, improves resource utilization, reduces writing latency, and improves product performance.

The invention discloses a method, device, equipment and medium for writing large block data of a solid-state hard disk. The method includes: screening large-block data write requests from write requests sent by the host; using a DM module to split the large-block data to be written corresponding to the large-block data write requests into multiple small-block data and mount them on a linked list; The DM module sends a write request to the LKM module, and the content of the write request includes the LBA first address of the large block of data to be written and the total number of small blocks of data; the LKM module receives the write request and performs cache allocation to generate several write request results Then return to the DM module; the DM module retrieves the context content of each small piece of data from the mounted linked list in units of small pieces of data according to the received several request results and initiates a data transfer request to the DMA module; in response to the DMA module completing the data If it is moved, the DM module resources and the LKM module resources are released. The scheme of the invention reduces the number of communication between modules, optimizes the efficiency of large block writing, reduces the writing delay, and increases the writing bandwidth.

Provided is a method of operating a resistive memory device including a memory cell array. The method includes the resistive memory device performing a first write operation in response to an active command and a write command and performing a second write operation in response to a write active command and the write command. The first write operation includes a read data evaluation operation for latching data read from the memory cell array in response to the active command. The second write operation excludes the read data evaluation operation.

The invention discloses a writing method for a resistive random access memory based on a crosspoint array, belonging to the field of information storage. The method of the invention increases effective voltage and reduces write delays by dynamically selecting the shortest voltage drop path; one regional division manner is employed to reduce differences among write delays in each area, so write delays in each area are reduced, and unit-level parallelism is guaranteed at the same time; the mapping between physical addresses and unit locations is established by employing an addressing mode, so write delays increase with the physical addresses, which facilitates optimization of address mapping, memory allocation and compilation; a parallel addressing circuit system is provided to speed up theaddressing process; and SET and RESET processes are overlapped for units in different rows and columns in virtue of a specific voltage bias mode, and row-level parallelism in the crosspoint array is developed. The method of the invention can reduce the write delays of the resistive random access memory, increase write bandwidth, and decrease the power consumption of writing.

The invention discloses a single side reading and writingstorage unit based on FinFET. The single side writing and reading storage unit comprises a first FinFET pipe, a second FinFET pipe, a third FinFET pipe, a fourth FinFET pipe, a fifth FinFET pipe, a sixth FinFET pipe, a seventh FinFET pipe, a position line, a character line, a character writing line, an upper-character writing line, a lower-character writing line and a dotted line, the first FinFET pipe and the second FinFET pipe are both P-type FinFET pipes, and the third FinFET pipe, the fourth FinFET pipe, the fifth FinFET pipe, the sixth FinFET pipe and the seventh FinFET pipe are all N-type FinFET pipes. The single side writing and reading storage unit has the advantages that on the basis of guaranteeing the reading operation stability, a high writing noise limit can be obtained, the storage value result is stable, the circuit function is stable, the leaked power consumption is small, the delay is also small, and data is quickly and stably accessed.

A data storage system includes a host having a write buffer, a memory region, a submission queue and a driver therein. The driver is configured to: (i) transfer data from the write buffer to the memory region in response to a write command, (ii) generate a write command completion notice; and (iii) send at least an address of the data in the memory region to the submission queue. The host may also be configured to transfer the address to a storage device external to the host, and the storage device may use the address during an operation to transfer the data in the memory region to the storage device.

Provided is a method of operating a resistive memory device including a memory cell array. The method includes the resistive memory device performing a first write operation in response to an active command and a write command and performing a second write operation in response to a write active command and the write command. The first write operation includes a read data evaluation operation for latching data read from the memory cell array in response to the active command. The second write operation excludes the read data evaluation operation.

The invention discloses an optimization method for improving PCM writing performance, which is characterized in that a flip bit and a plurality of flag bits are added to each PCM writing unit, the flip bit is used for marking whether corresponding data is subjected to a flipping operation or not, and the flag bits indicate whether all the data of the corresponding part is 0 or not. According to the method, the number of actually updated bits can be minimized, so that the service life of the PCM is prolonged.

The invention discloses a processing method, device and equipment for writing bulk data in a solid state disk and a medium. The method comprises the following steps: large data write requests are screened from write requests sent by a host; the DM module is used for splitting to-be-written large data corresponding to the large data writing request into multiple pieces of small data and mounting the small data to a linked list; the DM module sends a write request to the LKM module, wherein the content of the write request comprises an LBA initial address of large data to be written and the total number of small data; the LKM module receives the write request, performs cache allocation to generate a plurality of write request results and returns the write request results to the DM module; the DM module retrieves the context content of each piece of small data from the mounted linked list by taking the small data as a unit according to a plurality of received request results and initiates a data migration request to the DMA module; and the DM module resources and the LKM module resources are released in response to completion of data migration of the DMA module. According to the scheme, the number of communication times between modules is reduced, the efficiency of large block writing is optimized, the writing delay is reduced, and the writing bandwidth is improved.