Writing method for resistive random access memory based on crosspoint array

Abstract

The invention discloses a writing method for a resistive random access memory based on a crosspoint array, belonging to the field of information storage. The method of the invention increases effective voltage and reduces write delays by dynamically selecting the shortest voltage drop path; one regional division manner is employed to reduce differences among write delays in each area, so write delays in each area are reduced, and unit-level parallelism is guaranteed at the same time; the mapping between physical addresses and unit locations is established by employing an addressing mode, so write delays increase with the physical addresses, which facilitates optimization of address mapping, memory allocation and compilation; a parallel addressing circuit system is provided to speed up theaddressing process; and SET and RESET processes are overlapped for units in different rows and columns in virtue of a specific voltage bias mode, and row-level parallelism in the crosspoint array is developed. The method of the invention can reduce the write delays of the resistive random access memory, increase write bandwidth, and decrease the power consumption of writing.

Description

technical field [0001] The invention belongs to the field of information storage, and more particularly relates to a writing method of a resistive variable memory based on a cross-point array. Background technique [0002] DRAM has been used as memory for decades. However, it is difficult to further reduce the process of DRAM after it is reduced to tens of nanometers, and its cell access delay has been maintained at tens of nanoseconds and it is difficult to further reduce it. In addition, DRAM is a kind of volatile memory, and the energy consumption cost caused by its refresh operation cannot be ignored. These problems make it increasingly difficult to build large-capacity, low-latency, and low-power memory with DRAM. The emergence of emerging non-volatile memory has brought hope to the development of memory. Among them, resistive random-access memory (RRAM) is due to its smaller cell size (<10nm), longer write endurance (>10 10 cycles), higher on / off resistance r...

AI Technical Summary

Problems solved by technology

Therefore, the row-by-row region partitioning, addressing, and addressing schemes of traditional compatible DRAMs do not fully account for the uneven write latency distribution in cross-point arrays

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