The invention relates to a high performance DMA on an embedded type processor
chip. The high performance DMA comprises a
data buffer used for caching the data read from an on-
chip memory, the data sent to a
bus interface unit, the data received from the
bus interface unit, and the data written into the on-
chip memory; a data big-endian and little-endian convertor; a DMA controller used for initializing a state register, a
control register, an initial address register and a data size register; a DMA transmission address generating
logic module used for automatically calculating the transmission address of the next data on an on-chip external memory and generating chip selection and read and write signals of the on-chip memory according to the on-chip address, and simultaneously updating a data size counter till the counter changes to zero; and a
bus transmission
transmitter and
receiver. The high performance DMA has the advantages that the development difficulty is low, the cost of the hardware is low, the
transplantation is convenient, the expansibility is flexible, the
data transmission speed is high, and the performance of the processor is greatly enhanced.