Method for renaming state register and processor using the method

Abstract

The invention provides a method for renaming a status register in a superscalar processor with a pipeline structure, wherein the status register is a register composed of a plurality of flag bits selected from all flag bits of a flag register. The method comprises determining whether a microcode will read the status register when the microcode coded by a command reaches a register renaming module of the processor; if determining that the microcode will read the status register, allocating a nearest mapping physical register for the status register; otherwise, not allocating the physical register for the status register; determining whether the microcode will be written to the status register; if determining that the microcode will be written into the status register, allocating a new physical register with empty status to the status register; and otherwise, not allocating the physical register for the status register.

Description

technical field [0001] The present invention relates to microprocessor architecture, in particular to a method for renaming state registers in a processor with a superscalar pipeline structure and a processor using the method, which can rename the registers In order to improve the execution efficiency of the pipeline structure processor, the method can eliminate the false data correlation in the execution of the instruction, and can easily realize the renaming mechanism of the flag register to reduce the pipeline stall caused by reading and writing the flag bit. Background technique [0002] In the design of modern microprocessors, the throughput rate of instructions, that is, the number of instructions that can be executed per second, is a very important indicator. There are many ways to measure the number of instructions per unit time. The most direct technique is to increase the number of processors running However, an increase in frequency will lead to a rapid increase i...

AI Technical Summary

Problems solved by technology

[0004] A large number of modern processors use both pipeline and superscalar technologies to obtain higher performance. However, in practice, there may be some data dependencies between instructions, such as a The source operand that needs to be read by the instruction execution may be the value to be written by the previous instruction, such as they correspond to the same register, so the second instruction must wait until the previous instruction is executed and the result is written back to the register to continue

Images