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73results about How to "Optimal utilisation" patented technology

Cache device for coupling to a memory device and a method of operation of such a cache device

A cache device is provided for use in a data processing apparatus to store data values for access by an associated master device. Each data value has an associated memory location in a memory device, and the memory device is arranged as a plurality of blocks of memory locations, with each block having to be activated before any data value stored in that block can be accessed. The cache device comprises regular access detection circuitry for detecting occurrence of a sequence of accesses to data values whose associated memory locations follow a regular pattern. Upon detection of such an occurrence of a sequence of accesses by the regular access detection circuitry, an allocation policy employed by the cache to determine a selected cache line into which to store a data value is altered with the aim of increasing a likelihood that when an evicted data value output by the cache is subsequently written to the memory device, the associated memory location resides within an already activated block of memory locations. Hence, by detecting regular access patterns, and altering the allocation policy on detection of such patterns, this enables a reuse of already activated blocks within the memory device, thereby significantly improving memory utilisation, thereby giving rise to both performance improvements and power consumption reductions.
Owner:ARM LTD

Method for Modifying Mss

The invention refers to a method for optimising the data communication in a network comprising a wireless radio network using connection oriented protocol (TCP) over internet protocol (IP). The network comprises a router (SGSN) intervening the connection oriented setup between a host (SERVER) and a client (MS), and changing the maximum segment size (MSS, ms) into a maximum segment size (MSS, sgsn) based on the router's (SGSN) knowledge about the radio network.
Owner:TELEFON AB LM ERICSSON (PUBL)

Plate And Gasket For Plate Heat Exchanger

The invention relates to a heat exchanger plate for a plate heat exchanger, which plate has a number of ports, a distribution region, a heat transfer region, a first adiabatic region, a second adiabatic region and an edge area that extends outside the ports and the regions, which plate has a first gasket groove extending in the edge area outside the regions and around the ports, and a second gasket groove extending between the adiabatic region and the adjacent distribution region, whereby the gasket grooves are connected together to accommodate a gasket for sealing abutment against an adjacent heat exchanger plate in the plate heat exchanger. The invention further relates to a gasket for a heat exchanger plate and a plate heat exchanger having a package of heat exchanger plates and gaskets.
Owner:ALFA LAVAL CORP AB

Distributed computing network using multiple local virtual machines

A distributed computer system is disclosed in which computers co-operate with one another by sending messages over a network such as the Internet in order to perform a distributed application. In order to improve the security of such system, each web service involved in the distributed application runs in a separate virtual machine. Furthermore, the virtual machines on a web server dedicated to respective web service instances utilise the same policy enforcement point—running in another virtual machine on the web-server—in order to handle messages for or from the web server. To increase security still further, each virtual machine provides virtual cryptoprocessor functionality which is used in the processing of messages sent in the performance of the distributed application.
Owner:BRITISH TELECOMM PLC

Cache device for coupling to a memory device and a method of operation of such a cache device

A cache device is provided for use in a data processing apparatus to store data values for access by an associated master device. Each data value has an associated memory location in a memory device, and the memory device is arranged as a plurality of blocks of memory locations, with each block having to be activated before any data value stored in that block can be accessed. The cache device comprises regular access detection circuitry for detecting occurrence of a sequence of accesses to data values whose associated memory locations follow a regular pattern. Upon detection of such an occurrence of a sequence of accesses by the regular access detection circuitry, an allocation policy employed by the cache to determine a selected cache line into which to store a data value is altered with the aim of increasing a likelihood that when an evicted data value output by the cache is subsequently written to the memory device, the associated memory location resides within an already activated block of memory locations. Hence, by detecting regular access patterns, and altering the allocation policy on detection of such patterns, this enables a reuse of already activated blocks within the memory device, thereby significantly improving memory utilization, thereby giving rise to both performance improvements and power consumption reductions.
Owner:ARM LTD
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