36results about How to "Improving yield and reliability" patented technology

A current-leveling electrode for improving electroplating and electrochemical polishing uniformity in the electrochemical plating or electropolishing of metals on a substrate is disclosed. The current-leveling electrode includes a base electrode and at least one sub-electrode carried by the base electrode. The at least one sub-electrode has a width which is less than a width of the base electrode to impart a generally tapered, stepped or convex configuration to the current-leveling electrode.

Provided are a molecular electronic device and a method of fabricating the molecular electronic device. The molecular electronic device includes a substrate, an organic dielectric thin film formed over the substrate, a molecular active layer formed on the organic dielectric thin film and having a charge trap site, and an electrode formed on the molecular active layer. The organic dielectric thin film may be immobilized on the electrode or a Si layer by a self-assembled method. The organic dielectric thin film may include first and second molecular layers bound together through hydrogen bonds. An organic compound may be self-assembled over the substrate to form the organic dielectric thin film. The organic compound may include an M′-R-T structure, where M′, R and T represent a thiol or silane derivative, a saturated or unsaturated C1 to C20 hydrocarbon group which is substituted or unsubstituted with fluorine (F), and an amino(—NH2) or carboxyl (—COOH) group, respectively.

A chip package structure includes a circuit substrate, a chip, at least one bonding wire, and an adhesive layer. The circuit substrate has a bonding surface and at least one pad disposed on the bonding surface. The chip is disposed on the bonding surface of the circuit substrate and has an active surface away from the circuit substrate and at least one contact pad disposed on the active surface. The bonding wire is connected between the contact pad and the pad, such that the chip is electrically connected to the circuit substrate through the bonding wire. The bonding wire includes a copper layer, a nickel layer covering the copper layer, and a gold layer covering the nickel layer. The adhesive layer is disposed between the pad and the bonding wire and between the contact pad and the bonding wire and respectively covers two terminals of the bonding wire.

A method for manufacturing a semiconductor device includes forming an underlying layer over a semiconductor substrate; forming a hard mask layer over the underlying layer; forming first etch patterns over the hard mask layer; forming second etch patterns between the first photoresist patterns; etching the hard mask layer using the first and second etch patterns as an etch mask to form a hard mask pattern; and etching the underlying layer using at least the hard mask pattern. The first and second etch patterns are formed on the same layer.

An RRAM structure and its manufacturing method are provided. The RRAM structure includes a bottom electrode layer, a resistance switching layer, and an implantation control layer sequentially formed on a substrate. The resistance switching layer includes a conductive filament confined region and an outer region surrounding the conductive filament confined region. The RRAM structure includes a protective layer and a top electrode layer. The protective layer conformally covers the bottom electrode layer, the resistance switching layer, and the implantation control layer and has a first opening. The top electrode layer is located on the implantation control layer, and a portion of the top electrode layer is filled into the first opening. The position of the top electrode layer corresponds to that of the conductive filament confined region, and the top surface of the top electrode layer is higher than that of the protective layer.