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A frame for a heavy-duty vehicle includes a pail of spaced-apart, parallel, elongated, and longitudinally-extending main members. At least a pair of transverse cross members extend between and are attached to the main members, and each one of at least a pair of hangers is attached to and depends from a respective one of the main members and / or the cross members. A component is disposed between each one of the hangers and its respective main member, or alternatively is incorporated into the hangers, for absorbing the energy that is created by an extreme event during vehicle operation, to reduce the possibility of damage to the main members and / or the cross members caused by movement of at least one of the hangers during the extreme event.

A frame for a heavy-duty vehicle includes a pail of spaced-apart, parallel, elongated, and longitudinally-extending main members. At least a pair of transverse cross members extend between and are attached to the main members, and each one of at least a pair of hangers is attached to and depends from a respective one of the main members and / or the cross members. A component is disposed between each one of the hangers and its respective main member, or alternatively is incorporated into the hangers, for absorbing the energy that is created by an extreme event during vehicle operation, to reduce the possibility of damage to the main members and / or the cross members caused by movement of at least one of the hangers during the extreme event.

The present invention defines a system (100) for detecting copper contamination within a semiconductor manufacturing process. According to the present invention, a semiconductor wafer (102) is transferred (108) from a semiconductor manufacturing component (104), which may have exposed the wafer to copper contamination, to a measurement system (106). The measurement system measures an electrical value at a plurality of locations along a surface of the wafer, prior to and after exposure of the surface to an activation system (112). The activation system is provided to cause any copper contamination along the surface to form a precipitate thereon. An analysis component (110) is provided to receive electrical value and location information from the measurement system and to identify, from the measurements, the presence and location of copper contamination along the semiconductor wafer surface.

The present invention provides a system (200) for performing accelerated stress characterization of a given transistor (204). Inverter circuits, formed from the given transistor, are disposed in series with one another (202). A plurality of signal taps is operatively associated with each gap between adjacent inverter circuits. Selective circuitry is operatively coupled to the plurality of signal taps, and adapted to output (206) data from a first and a second of the plurality of signal taps. A controlled voltage component (212) is operatively coupled the plurality of inverter circuits, and adapted to supply a desired supply voltage. A controlled signal component (210) is operatively coupled the plurality of inverter circuits, and adapted to supply a signal of a desired frequency thereto. An evaluation component (208) receives signal data from the first and second signal taps for evaluation or processing.

The present invention provides a system for producing a triple-gate transistor segment (300), utilizing a standard semiconductor substrate (302). The substrate has a plurality of isolation regions (304) formed along its upper surface in a distally separate relationship, defining a channel region (306). A form structure (308) is disposed atop the isolation regions, and defines a channel body area (310) over the channel region. A channel body structure (316) is disposed within the channel body area, and is engineered to provide a blunted corner or edge (318) along a perimeter of its upper exposed surface. The form structure is then removed, and subsequent processing is performed.

The present invention provides a system (200) for controlling drive signal timing parameters of an output driver circuit (206). The present invention defines a driver circuit having an output interface (204), and a first transistor (222) coupled to a first voltage supply (230), a first control signal (232), and a first node (220). The circuit also has a first resistive element, coupled between the first node and a second node (234). A second resistive element (228) is coupled to ground. A second transistor (224) is coupled to the second node, to a second control signal (236), and the second resistive element. The circuit has a third transistor (244), coupled to the first and second nodes, and to a third node (240). A third resistive element (242) is coupled between the third node and the output interface. A fourth transistor (238) is coupled to the first and third nodes, and to the output interface. The circuit also has a fifth transistor (216), coupled to a second voltage supply (218), to the first node, and to the output interface.

The present invention provides a versatile system for controlling chemical mechanical polishing in a semiconductor manufacturing process. The system of the present inventions utilizes an in-situ chemical mechanical polishing system, having some type of measurement or metrology function, to bulk polish a semiconductor wafer to a first target threshold. Once the first target has been reached, a fuzzy logic control function, communicatively coupled to the in-situ chemical mechanical polishing system, takes control of further polishing. Measurement data from the measurement function is processed by the fuzzy logic control function, which then adjusts additional polishing time for the polishing system to render a desired wafer topography.

The present invention defines a system (200) for selectively controlling post-CMP dishing effects occurring in semiconductor wafers having copper metallization. The system has a CMP system (202) that performs copper overpolish and barrier polish on a copper-based semiconductor wafer (206). A profilometer (204) measures actual dishing occurring in the copper metallization after polishing. An input data set (220) includes a dishing target for the semiconductor wafer. A data integrity function (212) evaluates the profilometer's measurement, and generates an indicator of the reliability of the measurement. A modeling function (214) receives the measurement, the indicator, and the dishing target, and evaluates any differential between the dishing target and actual dishing. The modeling function generates a processing target to eliminate the differential, and modifies this process responsive to the indicator. A processing control function (210) receives the processing target, and alters the copper overpolish or barrier polish responsive to the processing target.

The present invention provides a system for reducing row periphery power consumption in a semiconductor memory device, particularly during sleep mode operation. A memory device (100) according to the present invention has a row (106) of memory cells and driver circuitry (102) preceding the row of memory cells. The present invention provides an intervention circuit (114) instantiated within the driver circuitry proximal to the row of memory cells. The intervention circuit is operated to hold the row of memory cells at a desired state, while the driver circuitry (108, 110) preceding the intervention circuit is powered down.

The present invention defines a system (100) for one-at-a-time paper clip dispensing. The system includes a housing (102), and a retrieval receptacle (114) disposed somewhere along the exterior of the housing. A storage component (104) is disposed along or within the housing, and is adapted to receive loose paper clips. A gate component (106) is operably coupled to the storage component, and a sorting component is incorporated within the storage or gate component(s). An actuating system (110) is disposed somewhere within or along the housing. A retrieval system (112) is disposed between the receptacle and the storage component. The retrieval system is adapted to retrieve a single paper clip from the gate component, and deliver the paper clip to the receptacle, responsive to activation of the actuating system.

The present invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage, frequency or current characteristics. The cross-lateral transistor is formed on a commercial semiconductor substrate (102). A channel structure (124) is formed along the substrate, having source (120) and drain (122) structures laterally formed on opposites sides thereof. A first gate structure (116) is formed along the substrate, laterally adjoining the channel structure orthogonal to the source and drain structures. A second gate structure (118) is formed along the substrate, laterally adjoining the channel structure, orthogonal to the source and drain structures and opposite the first gate structure.

A lockable MEMS switching architecture provided having a clutch assembly, a switching member, and an actuator. The clutch assembly has one or more engagement features located in proximity to the switching member—particularly one or more receiving features located upon the switching member. The clutch assembly is actuated to disengage the engagement features from the receiving features. The switching member is actuated to move in relation to the clutch assembly. Once the switching member is in a desired position, the clutch assembly is de-actuated, causing the engagement features to re-engage with the switching member, thereby restricting its further movement.

The present invention provides a system for electrostatic discharge protection in a semiconductor device, utilizing a silicon-controlled rectifier (502). The system includes the silicon controlled rectifier, which has a first p-type region (508) coupled to a voltage node (504), a first n-type region (512) having a first side adjoining the first p-type region, a second p-type region (510) having a first side adjoining a second side of the first n-type region, and a second n-type region (514) having a first side adjoining a second side of the second p-type region. A clamping structure (506) is intercoupled between the second n-type region and ground, to prevent the junction between the second p-type region and the second n-type region from retaining a forward bias. A switching structure (518) is intercoupled between the second p-type region and ground to ground the second p-type region during normal operation of the semiconductor device.

The present invention provides a system for removing organic contaminants (216) from a copper seed layer that has been deposited on a semiconductor substrate (206). The present invention provides a housing (204) to enclose the semiconductor substrate within. An ultraviolet radiation source (210) is disposed within the housing. A treatment medium (208) is also provided within the housing. The semiconductor substrate is enclosed within the housing and exposed to the treatment medium. The ultraviolet radiation source exposes the semiconductor substrate to ultraviolet radiation, desorbing the contaminants from the seed layer.

The present invention relates to an ejectable headlight device for replacement of one or more lightbulbs from the front of a vehicle. The lightbulb of the present invention has at least one lightbulb pin, an ejector, a base that houses the ejector and has at least one guide for receiving the lightbulb pin. The device has a release arm that engages the lightbulb pin. The device further includes a pivot point and a pull attached to the release arm. When the release arm secures the lightbulb pin to the base, the device is in the locked position. When the pull engages the release arm to put the device in the unlocked position, it allows the release arm to pivot about the pivot point and disengage the lightbulb pin. The present invention further includes methods, kits and systems utilizing same.