37results about "Logic circuits using saturable magnetic devices" patented technology

A logic signal isolator including a micro-transformer with a primary winding and a secondary winding. A transmitter circuit drives the primary winding in response to a received input logic signal such that, in response to a first type of edge in the logic signal, at least a first amplitude signal is supplied to the primary winding and, in response to a second type of edge in the logic signal, a second different amplitude signal is supplied to the primary winding. A receiver circuit receives corresponding first amplitude and second amplitude signals from the secondary winding and reconstructs the received logic input signal from the received signals.

The present invention is related to a a device and corresponding methods for generating an oscillating signal. The device comprises a means for providing a current of spin polarised charge carriers, a magnetic, e.g. ferromagnetic, excitable layer adapted for receiving the generated current of spin polarised charge carriers thus generating an oscillating signal with a frequency and an integrated means for interacting with said magnetic, e.g. ferromagnetic, excitable layer such that a selection of said oscillation frequency is achieved. No external field needs to be applied to select or tune the frequency. Different types of integrated means can be used, such as e.g. means inducing mechanical stress in the magnetic, e.g. ferromagnetic, excitable layer, means inducing exchange bias interactions and means inducing magnetostatic interactions.

A driver circuit drives data to an output based on an input data signal in a transmission mode. The driver circuit includes transistors. A comparator generates a comparison output in a calibration mode based on a reference signal and a signal at the output of the driver circuit. A calibration control circuit adjusts an equivalent resistance of the transistors in the driver circuit based on the comparison output in the calibration mode. The equivalent resistance of the transistors in the driver circuit can be adjusted to support the transmission of data according to multiple different data transmission protocols using transmission links having different characteristic impedances. The equivalent resistance of the transistors in the driver circuit can also be adjusted to compensate for resistance in the package routing conductors and / or to compensate for parasitic resistance.

Spin-orbital quantum cellular automata logic devices and integrated circuits in the form of a substrate having a thin film of material on the substrate having strongly coupled spin-orbital states, the thin film being patterned to define at least one input and at least one output, and to perform at least one logic operation by associated arrangement of the spin-orbital states between the input and the output. The logic devices and integrated circuits further include an input device at each input to define the spin-orbital states at each input, and an output sensor at each output for sensing the spin-orbital states of the thin film at the output. In an integrated circuit, the output of one gate or circuit, in the form of the ferromagnetically aligned spins, can be directly coupled to the next gate or circuit, so that entire circuits can be fabricated and effectively interconnected, only requiring interfacing for overall. circuit input and output using the electromagnetic inputs and magnetic measurements for the outputs.

One embodiment of a nonvolatile logic circuit includes a logic circuit comprising a first source terminal, a second source terminal, at least one input terminal, and an output terminal to temporarily store a logic state with a power dependent status, a high voltage source coupled to the first source terminal, a low voltage source coupled to the second source terminal, an intermediate voltage source comprising an electrical potential higher than that of the low voltage source but lower than that of the high voltage source, and a nonvolatile reversible resistance element coupled to the output terminal at a first end and to the intermediate voltage source at a second end. The nonvolatile reversible resistance element preserves the logic state of the logic circuit which is controlled by an input signal applied to the at least one input terminal. Other embodiment are described and shown.

Semiconductor industry seeks to replace traditional volatile logic and memory devices with the improved nonvolatile devices. The increased demand for a significantly advanced, efficient, and nonvolatile data retention technique has driven the development of magnetic tunnel junctions (MTJs) employing a giant magneto-resistance (GMR). The present application relates to nonvolatile logic circuits with integrated MTJs and, in particular, concerns a nonvolatile spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct the nonvolatile logic circuits performing NOT, NOR, NAND and other logic functions.

As a technique for attaining a reduction in power consumption, there is a technique for reducing power consumption using a spin wave. No specific proposal concerning spin wave generation, spin wave detection, and a latch technique for information has been made.A device applies an electric field to a first electrode of a nonmagnetic material using a thin line-shaped stacked body including a first ferromagnetic layer and a nonmagnetic layer to thereby generate a spin wave in the first ferromagnetic layer, and detects a phase or amplitude of the spin wave propagated in the first ferromagnetic layer using a second electrode of a ferromagnetic material with a magnetoresistance effect.

A nonvolatile full adder circuit comprising a full adder electrical circuitry comprising three input terminals for receiving two input and carry-in signals, a sum output terminal, and an carry-out output terminal; first and second nonvolatile memory elements electrically coupled to the first and second output terminal, respectively at their first ends and to an intermediate voltage source at their second ends. The nonvolatile memory elements comprise two stable logic states. A logic state each of the of the nonvolatile memory elements is controlled by a bidirectional electrical current running between its first and second ends. The full adder circuitry is electrically coupled to a high voltage source at its first source terminal and to a low voltage source at its second source terminal, wherein an electrical potential of the intermediate voltage source is lower than that of the high voltage source but higher than that of the low voltage source.

A frequency generator, includes a control unit, configured to receive an input signal to generate a divisor signal, a phase signal and a circulation signal; a frequency divider, configured to receive the input signal and perform an integer division to the input signal according to the divisor signal, so as to generate a frequency division signal; a circulating delay circuit, coupled to the frequency divider and configured to perform at least one circulating operation to the frequency division signal, and for each circulating operation, generate at least one phase delay signal; a first multiplexer, coupled to the circulating delay circuit and configured to select one signal from the frequency division signal and the at least one phase delay signal according to the phase signal, so as to generate a multiplexed signal; and a retimer, coupled to the first multiplexer and configured to generate an output signal.

To provide a logical operation circuit which can perform a logical operation using a ferroelectric capacitor and a logical operation method. A logical operation circuit 1 has a ferroelectric capacitors CF and a transistor MP. The ferroelectric capacitor CF can retain a polarization state P1 (y=1) or P2 (y=0) corresponding to first operation target data y. In an operation process, a first terminal 3 of the ferroelectric capacitor 1 is precharged to a source potential Vdd, and a potential corresponding to second operation target data x, that is, a ground potential GND (x=1) or the source potential Vdd (x=0), is given to a second terminal 5 of the ferroelectric capacitor via a bit line BL. When the threshold voltage Vth of the transistor MP is set properly, the transistor MP becomes on or off (on, on, on, off) depending on the combination of x and y (0-0, 0-1, 1-0, 1-1).

A non-volatile reconfigurable logic device executing logical operations and a memory function and controlled by a magnetic field is provided. The reconfigurable logic device includes i) at least one semiconductor device; and ii) a pair of magnetic field controlled devices respectively spaced apart from both sides of the semiconductor device and that are adapted to generate magnetic field leakage to control the semiconductor device. The semiconductor device includes i) a first semiconductor layer; and ii) a second semiconductor layer located on the first semiconductor layer. One of the first semiconductor layer and the second semiconductor layer is a p-type semiconductor layer and the other is an n-type semiconductor layer.

A driver circuit drives data to an output based on an input data signal in a transmission mode. The driver circuit includes transistors. A comparator generates a comparison output in a calibration mode based on a reference signal and a signal at the output of the driver circuit. A calibration control circuit adjusts an equivalent resistance of the transistors in the driver circuit based on the comparison output in the calibration mode. The equivalent resistance of the transistors in the driver circuit can be adjusted to support the transmission of data according to multiple different data transmission protocols using transmission links having different characteristic impedances. The equivalent resistance of the transistors in the driver circuit can also be adjusted to compensate for resistance in the package routing conductors and / or to compensate for parasitic resistance.

As a technique for attaining a reduction in power consumption, there is a technique for reducing power consumption using a spin wave. No specific proposal concerning spin wave generation, spin wave detection, and a latch technique for information has been made.A device applies an electric field to a first electrode of a nonmagnetic material using a thin line-shaped stacked body including a first ferromagnetic layer and a nonmagnetic layer to thereby generate a spin wave in the first ferromagnetic layer, and detects a phase or amplitude of the spin wave propagated in the first ferromagnetic layer using a second electrode of a ferromagnetic material with a magnetoresistance effect.

A magnetic logic element with toroidal magnetic multilayers (5,6,8,9). The magnetic logic element comprises a toroidal closed section which is fabricated by etching a unit of magnetic multilayers (5,6,8,9) deposited on a substrate. Optionally, the magnetic logic element may also comprise a metal core (10) in the closed toroidal section. Said magnetic multilayers (5,6,8,9) unit is arranged on the input signal lines A, B, C and an output signal line O, and then is made into a closed toroidal. Subsequently, on the toroidal magnetic multilayered unit (5,6,8,9), the input signal lines A′, B′, C′ and an output signal line O′ are fabricated by etching. This magnetic logic element can reduce the demagnetization field and the shape anisotropy effectively, leading to the decrease of the reversal field of magnetic free layer. Furthermore, this magnetic logic element has stable working performance and long operation life of the device.

The technical subject of the present invention is to provide a novel magnetic logic element which is small and can perform logic processing, and magnetic logic element array formed by arrange the device in an array. The means to solve the said technical subject of the present invention is to provide a magnetic logic element comprising: at least two magnetic layers (HM, SM); an intermediate portion (SP) between the magnetic layer; and the magnetization direction controlling portion of the magnetic layer (SM); and more than two input signals A, B for controlling the magnetization direction of the magnetic layer (SM), which are assigned with logic 0, 1 to determine the magnetization of the magnetic layer (SM) by the configuration of the input signals A, B. The magnitude of the magnetoresistance effect of the intermediate portion inbetween is the output signal C.

A method and system for providing a logic device are described. The logic device includes a plurality of magnetic input / channel regions, at least one magnetic sensor region, and at least one sensor coupled with the at least one magnetic sensor region. Each of the magnetic input / channel regions is magnetically biased in a first direction. The magnetic sensor region(s) are magnetically biased in a second direction different from the first direction such that at least one domain wall resides in the magnetic input / channel regions if the logic device is in a quiescent state. The sensor(s) output a signal based on a magnetic state of the magnetic sensor region(s). The input / channel regions and the magnetic sensor region(s) are configured such that the domain wall(s) may move into the magnetic sensor region(s) in response to a logic signal being provided to at least a portion of the magnetic input regions.

A signal-transferring device having a first circuit and a second circuit that operate on different ground references, and a third circuit for transferring signals while providing insulation between the first circuit and the second circuit. The second circuit switches a logic level of an output signal in accordance with the logic level of an input signal notified by the first circuit, and notifies the first circuit about the logic level of the output signal. The first circuit notifies the second circuit about the logic level of the input signal not only when the logic level of the input signal has been switched, but also when the logic level of the output signal notified by the second circuit does not match the logic level of the input signal.

A driving system and method to effect propagation of a magnetic domain wall through a ferromagnetic conduit are described, wherein oscillating electrical current is passed through the conduit from an oscillating current supply source via at least two electrical contacts adapted to make electrical connection with at least two spaced points on the conduit. A ferromagnetic conduit is described comprising an elongate ferromagnetic element formed as a continuous track of magnetic material capable of sustaining and propagating a domain wall, and such a driving system in serial array, preferably being further adapted to serve as a magnetic logic element by the provision of nodes and / or directional changes as a result of which logical functions may be processed.

Disclosed is a magnetic logic device including: a plurality of input branches configured by a magnetic nanowire including a non-magnetic metallic layer, a free layer, and an insulating layer sequentially stacked; an output branch configured by the magnetic nanowire; a coupling portion configured by the magnetic nanowire and where the input branches and the output branch meet; gate electrodes arranged adjacent to the insulating layer in each of the plurality of input branches; and in-plane anisotropic ferromagnetic layers arranged adjacent to the non-magnetic metallic layer in each of the plurality of input branches.