730results about "Elastomeric polymer dielectrics" patented technology

Disclosed herein are stretchable, foldable and optionally printable, processes for making devices and devices such as semiconductors, electronic circuits and components thereof that are capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Strain isolation layers provide good strain isolation to functional device layers. Multilayer devices are constructed to position a neutral mechanical surface coincident or proximate to a functional layer having a material that is susceptible to strain-induced failure. Neutral mechanical surfaces are positioned by one or more layers having a property that is spatially inhomogeneous, such as by patterning any of the layers of the multilayer device.

In an aspect, the present invention provides stretchable, and optionally printable, components such as semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed, and related methods of making or tuning such stretchable components. Stretchable semiconductors and electronic circuits preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention are adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

The present invention relates to stretchable interconnects which can be made in various geometric configurations, depending on the intended application. The stretchable interconnects can be formed of an electrically conducting film or an elastomer material to provide elastic properties in which the interconnects can be reversibly stretched in order to stretch and relax the elastomer material to its original configuration. Alternatively, stretchable interconnects can be formed of an electrically conducting film or a plastic material to provide stretching of the material to a stretched position and retaining the stretched configuration. The stretchable interconnect can be formed of a flat 2-dimensional conductive film covering an elastomeric or plastic substrate. When this structure is stretched in one or two dimensions, it retains electrical conduction in both dimensions. Alternatively, the stretchable and/or elastic interconnects can be formed of a film or stripe that is formed on an elastomeric or plastic substrate such that it is buckled randomly, or organized in waves with long-range periodicity. The buckling or waves can be induced by various techniques, including: release of built-in stress of the conductive film or conductive stripe; pre-stretching the substrate prior to the fabrication of the conductive film or conductive stripe; and patterning of the surface of the substrate prior to the fabrication of the metal film. The stretchable interconnect can be formed of a plurality of conductive films or conductive stripes embedded between a plurality of layers of a substrate formed of an elastomer or plastic.

A flexible and stretchable patterned substrate is provided having a strain-permitting material comprising a patterned conformation that allows the flexible patterned substrate to experience local strain or local strain domains lower than the macroscopic strain of the flexible and stretchable patterned substrate.

A microelectronic package includes a microelectronic element having faces and contacts, a flexible substrate overlying and spaced from a first face of the microelectronic element, and a plurality of conductive terminals exposed at a surface of the flexible substrate. The conductive terminals are electrically interconnected with the microelectronic element and the flexible substrate includes a gap extending at least partially around at least one of the conductive terminals. In certain embodiments, the package includes a support layer, such as a compliant layer, disposed between the first face of the microelectronic element and the flexible substrate. In other embodiments, the support layer includes at least one opening that is at least partially aligned with one of the conductive terminals.

The present invention provides an electrically conductive adhesive composition having cured low modulus elastomer and metallurgically-bonded micron-sized metal particles and nano-sized metal particles. The low modulus elastomer provides the mechanical robustness and reliability by relieving the stresses generated; and the metallurgically-bonded micron-sized metal particles and nano-sized metal particles provide a continuous conducting path with minimized interface resistance. Addition of nano-sized metal particles lowers the fusion temperature and allows the metallurgical-bonding to occur at manageable temperatures.

An anisotropic conductive adhesive contains conductive particles dispersed in a resin composition, wherein the resin composition includes a radical polymerization resin (A), an organic peroxide (B), a thermoplastic elastomer (C) and a phosphoric ester (D). The resin composition can further contain an epoxy silane coupling agent (E) represented by formula (2) or (3). The resin composition is mixed with other components after the radical polymerization resin (A), the thermoplastic elastomer (C), the phosphoric ester (D) and the epoxy silane coupling agent (E) are reacted. It is also possible to preliminarily react only the phosphoric ester (D) and the epoxy silane coupling agent (E) and to react the product of the preliminary reaction with the radical polymerization resin (A) and the thermoplastic elastomer (C), and then to add other components. The anisotropic conductive adhesive of the present invention can be used for electrical joining of electronic or electric parts of electrical apparatus.

A resin composition which is low in a roughness of an insulating layer surface and capable of forming thereon a plated conductor layer having a sufficient peel strength in a wet roughing step and which is excellent in dielectric characteristics and a coefficient of thermal expansion, is disclosed. The resin composition contains a cyanate ester resin and a specified epoxy resin.

A prepreg for a printed wiring board, comprising a cyanate ester resin having a specific structure, a non-halogen epoxy resin, a silicone rubber powder as a rubber elasticity powder, an inorganic filler and a base material, which prepreg retains heat resistance owing to a stiff resin skeleton structure, has high-degree flame retardancy without the use of a halogen compound or a phosphorus compound as a flame retardant, and has a small thermal expansion coefficient in plane direction without using a large amount of inorganic filler, and a laminate comprising the above prepreg.

A high performance electrical interconnect adapted to provide an interface between terminals on first and second circuit members. The electrical interconnect includes a first circuitry layer with a first surface and a second surface having a plurality of contact pads adapted to electrically coupled with the terminals on the first circuit member. At least one dielectric layer is printed on the first surface of the first circuitry layer. The dielectric layer includes a plurality recesses. A conductive material is deposited in at least a portion of the recesses to create circuit geometry electrically coupled with the first circuitry layer. A second circuitry layer includes a first surface a plurality of contact pads adapted to electrically couple with the terminals on the second circuit member and a second surface attached to the dielectric layers. The circuit geometry electrically couples the first circuitry layer to the second circuitry layer.

In an aspect, the present invention provides stretchable, and optionally printable, components such as semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed, and related methods of making or tuning such stretchable components. Stretchable semiconductors and electronic circuits preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention are adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

A packaged semiconductor chip including the chip, and a package element such as a heat sink is made by connecting flexible leads between contacts on the chip and terminals on a dielectric element such as a sheet or plate and moving the sheet or plate away from the chip, and injecting a liquid material to form a compliant layer filling the space between the package element and the dielectric element, and surrounding the leads. The dielectric element and package element extend outwardly beyond the edges of the chip, and physically protect the chip. The assembly may be handled and mounted by conventional surface mounting techniques. The assembly may include additional circuit elements such as capacitors used in conjunction with the chip.

An electrical interconnect for providing a temporary interconnect between terminals on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a substrate with a first surface having a plurality of openings arranged to correspond to the terminals on the IC device. A compliant material is located in the openings. A plurality of conductive traces extend along the first surface of the substrate and onto the compliant material. The compliant material provides a biasing force that resists flexure of the conductive traces into the openings. Conductive structures are electrically coupled to the conductive traces over the openings. The conductive structures are adapted to enhance electrical coupling with the terminals on the IC device. Vias electrically extending through the substrate couple the conductive traces to PCB terminals located proximate a second surface of the substrate.

Reliability of circuit packaging while accommodating larger chips and increased temperature excursions is achieved by use of compliant pads only at the locations of connections between packaging levels, preferably between a laminated chip carrier and a printed circuit board. The invention allows the coefficient of thermal expansion of the chip carrier to be economically well-matched to the CTE of the chip and accommodation of significant differences in CTEs of package materials to be accommodated at a single packaging level. The compliant pads are preferably of low aspect ratio which are not significantly deflected by accelerations and can be formed on a surface or recessed into it. Connections can be made through surface connections and/or plated through holes. Connection enhancements such as solder wettable surfaces or dendritic textures are provided in a conductive metal or alloy layer over a compliant rubber or elastomer layer which may be conductive or non-conductive.

An assembly includes a structure, a plurality of terminals and a plurality of compliant pads disposed between said terminals and said structure. The terminals are aligned with at least some of said pads, with the pads providing a standoff between the structure and the terminals. The compliant pads are preferably made of a non-conductive material such as a silicone elastomer.

An electronic patch includes a foldable circuit layer that includes a foldable network that includes comprising: a plurality of electronic modules comprising a plurality of electronic components, and flexible straps that connect the plurality of electronic modules, wherein the flexible straps comprise conductive circuit that are conductively connected with the plurality of electronic components in the plurality of electronic modules. Neighboring electronic modules can undulate in opposite directions normal to the foldable circuit layer. The electronic patch also includes an elastic layer that encloses the foldable circuit layer.