166results about "Coding bounds" patented technology

An approach is provided for a method of encoding structure Low Density Parity Check (LDPC) codes. Memory storing information representing a structured parity check matrix of Low Density Parity Check (LDPC) codes is accessed during the encoding process. The information is organized in tabular form, wherein each row represents occurrences of one values within a first column of a group of columns of the parity check matrix. The rows correspond to groups of columns of the parity check matrix, wherein subsequent columns within each of the groups are derived according to a predetermined operation. An LDPC coded signal is output based on the stored information representing the parity check matrix.

An approach is provided for bit labeling of a signal constellation. A transmitter generates encoded signals using, according to one embodiment, a structured parity check matrix of a Low Density Parity Check (LDPC) code. The transmitter includes an encoder for transforming an input message into a codeword represented by a plurality of set of bits. The transmitter includes logic for mapping non-sequentially (e.g., interleaving) one set of bits into a higher order constellation (Quadrature Phase Shift Keying (QPSK), 8-PSK, 16-APSK (Amplitude Phase Shift Keying), 32-APSK, etc.), wherein a symbol of the higher order constellation corresponding to the one set of bits is output based on the mapping.

Methods and apparatus for designing spherical lattice codebooks for use in data transmission systems are provided. A spherical lattice codebook is constructed by determining the channel statistics of one or more channels, which can be accomplished by observing a sufficiently large set of channel realizations. After determining the channel statistics, an expression for the error probability of the decoder or expressions for bounds on the error probability and expressions for the corresponding gradients are determined. The gradient is then used in an optimization technique to produce a spherical lattice codebook which is subsequently used for transmission.

A method of mobile communication including a transmitter having multiple transmitters and a receiver having multiple receivers. The method includes adding a cyclic redundancy check (CRC) code to a data block to be transmitted and spatially segmenting the data block according to a modulation scheme and a coding rate of each respective transmit antenna of the multiple antennas.

In this parity data generating circuit, a Galois field multiplying calculation is realized by performing data conversion by index table information generated from a Galois field multiplying table so that data for RAID6 are generated. A table check circuit inspects nonconformity of the index table information in advance by using results in which the Galois field multiplying table is indexed from different directions constructed by the longitudinal direction and the transversal direction. Data and parity for making the multiplying calculation are decomposed into plural data and parities by using this table check circuit, and index table information different from each other are allocated to these data and parities. Thus, a longitudinal index table making circuit and a transversal index table making circuit themselves are checked.

A method and apparatus for generating and inserting bit errors in data words that have been encoded in a forward error correction (FEC) system in order to estimate power dissipation. In accordance with the present invention, it has been determined that a burst error generator that is capable of erroring the maximum number of correctable data bits in every FEC encoded frame, which allows the designer to accurately produce test vectors that are suitable for use in commercially available power estimation tools. In addition, after the IC is produced, the burst error generator of the present invention can be enabled to provide real-time FEC power dissipation data for use in system thermal modeling, thus obviating the need to use costly external devices that emulate a given error rate. Furthermore, the power dissipation data obtained in real-time may be used to refine the initial design power estimate, which will then allow the designer to develop a more accurate prediction of power consumption for future IC designs. Thus, the burst error generator of the present invention is capable of reducing iterations of IC designs by accurately estimating the worst-case power dissipation of FEC decoders.

In one embodiment, a memory controller comprises a cache line processing block for processing a cache line into a plurality of segments, an error correction code (ECC) generation block that forms ECC code words for each of the plurality of segments for storage in a plurality of memory components, an ECC correction block for correcting at least one single-byte erasure error in each erasure corrupted ECC code word retrieved from the plurality of memory components, and an error seeding block that enables a respective error to be inserted into each ECC code word of the cache line in response to a plurality of error registers.

A qubit generating unit generates a qubit having a predetermined quantum state. A qubit encoding unit performs quantum encoding of the generated qubit. A first pseudo-random number generating unit generates a first pseudo-random number from secretly shared information, which has been secretly shared with the quantum receiving device in advance. A quantum modulator performs quantum modulation of the qubit on which quantum encoding has been performed based on the first pseudo-random number and sends the modulated qubit to the quantum receiving device. A second pseudo-random number generating unit generates a second pseudo-random number from secretly shared information which has been secretly shared with the above quantum sending device in advance synchronously with generation of the above first pseudo-random number. A qubit demodulator performs quantum demodulation of the qubit, which has been received from the quantum demodulator based on the second pseudo-random number,

A test method for a semiconductor device that is provided with an ECC circuit that uses product code that is composed of a first code and a second code for implementing error correction of a memory, the test method includes steps of: obtaining first pass / fail determination results and second pass / fail determination results that are realized by independent correction operations based on the first code and the second code, respectively; recording the results in a first fail memory and a second fail memory, respectively; executing a prescribed logical operation such as an AND operation relating to the contents of the first fail memory and the contents of the second fail memory; and based on the results of the logical operation, remedying both fail bits and potential fail bits.

The loss of packets in a communication system can be minimized in an optimal manner by adapting a set of error correction (EC) parameters in response to a calculated probability of packet loss. The calculated probability is obtained from derived algorithms that are applied to a set of communication parameters. Algorithms are derived from Bernoulli-distributed traffic models and constant bit rate (CBR) traffic models of the communication system. A collapsed-state model is used to derive a very efficient algorithm that calculates an approximate probability of packet loss. Alternate applications for the algorithms are also disclosed.

A scrambling code generating apparatus of a downlink transmitter in a UMTS mobile communication system, which uses one primary scrambling code for separation of base stations and multiple secondary scrambling codes for channel separation. The apparatus includes a first m-sequence generator for generating a first m-sequence and a second m-sequence generator for generating a second m-sequence. A first summer adds the first and second m-sequences to generate the primary scrambling code. A plurality of first masking sections each shift the first m-sequence, and a plurality of second masking sections corresponding to the respective first masking sections each shifts the second m-sequence. A plurality of second summers each adds one of the first shifted m-sequences with the second m-sequence corresponding to the first m-sequence. The output of the second summers thus generates the multiple secondary scrambling codes.

An encoder includes an outer repetition encoder, an interleaver for permuting encoding from said outer repetition encoder; and an inner encoder for encoding information from the interleaver to provide a repeat zigzag-Hadamard code. In an exemplary embodiment, a common bit of a zigzag-Hadamard segment of encoding from said inner encoder is a repetition of a last parity bit of a previous zigzag-Hadamard segment of encoding from said inner encoder and said common bit is punctured.

Method for evaluating the performance of different forward error correction codes in communication systems which require low bit error rates, in particular in optical transmission systems, comprising: receiving from a transmission channel uncoded data symbols; separating a codeword vector and a noise vector, so that the noise vector is dependent on the transmitted data when non-linear effects occur; encoding known data bits using a parity check matrix of the code to obtain parity symbols; adding the noise vector to the encoded bits; and providing the performance of the forward error correction for ex¬ ample by counting errors.