220 results about "Pattern space" patented technology

A large area dummy pattern DL is formed in a layer underneath a target T2 region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds2 in an upper layer are disposed in a region where the inter-pattern space of a pattern (active regions L1, L2, L3, gate electrode 17), which functions as an element of a product region PR and scribe region SR, is wide. The small area dummy pattern Ds2 in the upper layer is offset by ½ pitch relative to the small area dummy pattern Ds in the lower layer.

A bend-detecting (bending) sensor is provided, including a flexible substrate, at least a pair of electrode patterns spaced apart from each other provided on the flexible substrate, and a paste layer containing conductive particles. The paste layer is coated onto the flexible substrate where the electrode patterns are formed, such that when the flexible substrate is bent, the density of the conductive particles between the electrode patterns changes and an electric resistance between the electrode patterns also changes, thereby sensing deformation of the flexible substrate, and eventually, a target to which the flexible display element or the flexible substrate is attached. When the bending sensor is applied to the flexible display device, the electrode patterns and the paste layer may be formed on the flexible substrate which is to form the flexible display element, thus forming a bending sensing structure with a thickness of the flexible display element or less.

A method of manufacturing a thin film transistor that provides high electric field mobility is disclosed. The method comprising: a) forming an amorphous silicon layer and a blocking layer on an insulating substrate; b) forming a photoresist layer having first and second photoresist patterns on the blocking layer, the first and second photoresist patterns spaced apart from each other; c) etching the blocking layer using the first photoresist pattern as a mask to form first and second blocking patterns; d) reflowing the photoresist layer, so that the first and second photoresist patterns abut on each other to entirely cover the first and second blocking patterns; e) forming a metal layer over the entire surface of the insulating substrate; f) removing the photoresist layer to expose the blocking layer and an offset region between the blocking layer and the metal layer; g) crystallizing the amorphous silicon layer to form a poly silicon layer, wherein a portion of the amorphous silicon layer directly contacting the first metal layer is crystallized through a metal induced crystallization (MIC), and the remaining portion of the amorphous silicon layer is crystallized through a metal induced lateral crystallization (MILC), so that a MILC front exists on a portion of the poly silicon layer between the first and second blocking patterns; h) etching the poly silicon layer using the first and second blocking patterns as a mask to form first and second semiconductor layers and to remove the MILC front; and i) removing the first and second blocking patterns.

A display device that can reduce color shift and prevent the quality of an image from degrading due to Moire. The display device includes a display panel and an optical film, which includes a background layer disposed in front of the display panel, and a lens section formed on the background layer. The lens section has a plurality of patterns spaced apart from each other to diffuse incident light. The spacing [tau] and pitch T of the patterns are determined by the following m value in the following formulae, and m = P / T, p / P is an aperture ratio of sub-pixels of the display panel, [tau] / T is an aperture ratio of the lens section, I is an intensity of light exiting the optical film after being diffused through the sub-pixels, P and p are a pitch and a width of the sub-pixels, T is a pitch of the patterns, and [tau]=T-W.