37 results about "Nibble" patented technology

A memory module substrate printed-circuit board (PCB) has multi-type footprints and an edge connector for mating with a memory module socket on a motherboard. Two or more kinds of dynamic-random-access memory (DRAM) chips with different data I / O widths can be soldered to solder pads around the multi-type footprints. When ×4 DRAM chips with 4 data I / O pins are soldered over the multi-type footprints, the memory module has a rank-select signal that drives chip-select inputs to all DRAM chips. When ×8 DRAM chips with 8 data I / O pins are soldered over the multi-type footprints, the memory module has two rank-select signals. One rank-select drives chip-select inputs to front-side DRAM chips while the second rank-select drives chip-select inputs to back-side DRAM chips. Wiring traces on the PCB cross-over data nibbles between the solder pads and the connector to allow two ×4 chips to drive a byte driven by only one ×8 chip.

Reading and writing data from a plurality of memory devices. A code word having a plurality of bits is partitioned into nibbles. Adjacent nibbles are stored on a common physical medium. The failure of the common physical medium results in errors in adjacent nibbles of a reconstructed code word.

A method and apparatus for encoding a sequence of 32 bit digital data words into a sequence of 33 bit code words in consonance with predetermined minimum zero run length (d) and predetermined maximum zero run length (k) for recording upon a magnetic medium within a magnetic recording channel is disclosed. The method comprises steps of dividing each data word into eight data nibbles, determining whether any data nibble contains all zeros. If no code violation, mapping the eight data nibbles to seven code nibbles and to four bits of a five bit code sub-word and setting a fifth control bit to one. If one or more code violations are present, embedding code violation locations within at least the five bit code sub-word and other code nibbles if necessary and remapping data nibbles ordinarily directed to the code sub-word and nibble locations to code locations otherwise containing the data nibbles determined to be code violations.

A memory system provides data error detection and correction and address error detection. A cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to 6 address check bits using the CRC code. The 6 address check bits are concatenated with 64 data bits and 2 flag bits to generate a 72-bit check word. The 72-bit check word is input to an error-correction code (ECC) generator that generates 12 check bits that are stored in memory with the 64 data bits. A 76-bit memory module can store the 64 data and 12 check bits. Nibble errors can be corrected, and all nibble+1 bit errors can be detected. Also, a 6-bit error in a sequence of bits can be detected. This allows all errors in the 6-bit CRC of the address to be detected. The CRC code and ECC are ideal for detecting double-bit errors common with multiplexed-address DRAMs.

Error correction coding is provided for codeword headers in a data tape format, such as a Linear Tape-Open, Generation 4 (LTO-4) data tape format. The data tape format defines a codeword quad as having first and second codeword headers interleaved with first and second codeword pairs, each codeword header comprising N bytes Ck=C0, C1, . . . , CN−2, CN−1 wherein K bytes C0-CK−1 of the first and second headers in a codeword quad differ such that if one is known the other can be inferred. Each header byte Ck of a codeword quad is redefined as comprising two interleaved (M / 2)-bit nibbles, ek, ok. For each header, nibbles ek-eN−1 and nibbles ok-oN−1 are generated as a function of nibbles, e0-EK−1 and o0-oK−1, respectively. A codeword is assembled with the redefined headers the codeword quad is then recorded onto a recording medium.

A line card for use in a node of a network to connect to optical network lines is provided. The line card includes an optical interface, and a serializer / deserializer (SERDES) operating at a first frequency. The line card also includes a framer operating at a second frequency where the first frequency is higher than the second frequency. The framer includes a digital step up converter to receive data from the SERDES and a digital step down converter to supply data to the SERDES. The step down converter includes a set of input buffers where each input buffer receives a word of nibbles from the framer. The input buffers are loaded one after another, but extraction from each of the input buffers to a multi-stage multiplexer is triggered so long as a non-reset window is preserved. The step up converter includes a set of input buffers and a register array where each input buffer receives a word of nibbles from the register array. The input buffers are loaded one after another, but extraction from the input buffers to a multi-stage multiplexer is triggered so long as a non-reset window is preserved.

A recording and reproducing system is broken down into a recording unit for producing a digital audio data signal from MIDI music data words asynchronously produced at irregular intervals and a playback unit for reproducing the MIDI music data codes from the digital audio data signal, wherein synchronous data nibbles are supplemented in the irregular intervals among the MIDI music data words for producing a data stream, and the digital audio data signal is produced from the data stream through a differential phase shift keying and a phase code modulation so as to record the MIDI messages in a digital versatile disk at high dense.

A method and system for secure call Dual-Tone Multi-Frequency (DTMF) signaling includes entering (202) dial string of a telephone number of a destination device, assigning (210, 212) the dial string to a predefined string having a total length that is greater than the dial string such that there will be at least one leading hexadecimal bit in the predefined string length that is not used when the entered dial string is converted to a hexadecimal, converting (214) the dial string to hexadecimal, reversing the order of the hexadecimal, and placing the reversed hexadecimal at the beginning of the predefined string, appending (216) “one” bits to the predefined string length indicating how many nibbles of the predefined string length are unused, if any, and appending the remaining intervening unused bits in the predefined string length to “zero” bits, and sending (226) the encoded string length.

Each packet normally consists of a preamble, start-of-frame delimiter and data. The preamble has nibbles each having a particular format. A header substituted for preamble nibbles by an individual one of the originating devices in a plurality, and an individual one of the ports in such originating device, indicates such originating device and such port. Such port in such originating device sends such modified packet to others of the originating devices and to an observing station. The header format is such that the last nibble in the header and the remaining preamble portion will not be confused with any two (2) nibbles in the header. A particular one of the originating devices indicated in the data converts the header back to the preamble format and transmits the converted packet to a receiving station. The observing station records the individual originating device, and the individual port in such device, indicated in the header. Each packet includes at its end a trailer formed from a plurality of nibbles and indicating whether or not a collision has occurred between such packet and a packet from another one of the originating devices. The trailer in each packet may also indicate additional information—e.g. whether the packet (a) is a normal packet originally formed, (b) is a runt packet, (c) is from an unacceptable source and (d) the delay between each packet end and the next packet start. The information in the trailer for each packet passes to the observing station.

A hybrid serial / parallel bus interface for a base station has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block.

A hybrid serial / parallel bus interface for a user equipment (UE) has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block.

The invention relates to error correction coding methods, methods and systems for error correction. Error correction coding is provided for codeword headers in a data tape format, such as a Linear Tape-Open, Generation 4 (LTO-4) data tape format. The data tape format defines a codeword quad as having first and second codeword headers interleaved with first and second codeword pairs, each codeword header comprising N bytes Ck=C0, C1, . . . , CN-2, CN-1 wherein K bytes C0-CK-1 of the first and second headers in a codeword quad differ such that if one is known the other can be inferred. Each header byte Ck of a codeword quad is redefined as comprising two interleaved (M / 2)-bit nibbles, ek, ok. For each header, nibbles ek-eN-1 and nibbles ok-oN-1 are generated as a function of nibbles, e0-EK-1 and o0-oK-1, respectively. A codeword is assembled with the redefined headers the codeword quad is then recorded onto a recording medium.

The invention discloses a serial port communication error detection and correction method and device, belonging to the field of serial port communication. The present invention improves on the basis of the Hamming code, including: receiving a serial communication data frame, the serial communication data frame including two data bytes and a sending end check byte; forming the sending end check byte The two nibbles are the verification results of the first data byte and the second data byte respectively, and each bit of the first data byte and the second data byte has passed at least two bits of verification Check the bit; generate the check byte of the receiving end, and form each check bit of the check byte of the receiving end to generate according to one check bit of the data byte and the check byte of the sending end; according to the Check bytes at the receiving end for error detection and error correction. This overcomes the problem that the position of the traditional Hamming code check code is fixed and the overall length cannot be sent through the serial port, and can accurately correct the wrongly transmitted data, which is simple and reliable.

A hybrid serial / parallel bus interface method for a base station has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block.