157 results about "Blocking oscillator" patented technology

Local oscillator circuitry for an antenna array is disclosed. The circuitry includes an array of rotary traveling wave oscillators which are arranged in a pattern over an area and coupled so as to make them coherent. This provides for a set of phase synchronous local oscillators distributed over a large area. The array also includes a plurality of phase shifters each of which is connected to one of the rotary oscillators to provide a phase shifted local oscillator for the array. The phase shifter optionally includes a cycle counter that is configured to count cycles of the rotary oscillator to which it is connected and control circuitry that is then operative to provide a shifted rotary oscillator output based on the count from the cycle counter. A system and method for operating a true-time delay phased array antenna system. The system includes a plurality of antenna element circuits for driving or receiving an rf signal from the elements of the array. Each element circuit has a transmit and a receive path and a local multiphase oscillator, such as a rotary traveling wave oscillator. Each path has an analog delay line for providing a true-time delay for the antenna element. Preferably, the analog delay line is a charge coupled device whose control nodes are connected to phases of the local multiphase oscillator to implement a delay that is an integer number local multiphase oscillator periods. A fractional delay is also included in the path by using a sample and hold circuit connected to a particular phase of the oscillator. By delaying each antenna element by a true time delay, broadband operation of the array is possible.

A method of measuring the transistor leakage current. In one embodiment, the method involves driving a ring oscillator with a dynamic node driver having a leakage test device biased to an off state to produce a test signal. The test signal is extracted and the frequency is measured. The leakage current is estimated from the measured frequency.

A heterodyne communication system uses coherent data modulation that is resistant to phase noise. In particular, a pilot tone and reference clock signal are transmitted along with the modulated data to form the basis of an electrical demodulation local oscillator at the receiver. The pilot tone and/or reference clock signal carry phase noise which is correlated with the phase noise in the data signal. At the receiver, the local oscillator is generated from the pilot tone and reference clock signal in a manner so that the local oscillator also has phase noise which is correlated with the phase noise in the data signal. Thus, the two noise components can be used to cancel each other during demodulation of the data signal using the local oscillator.

An oscillating signal of relatively precise frequency is generated by tuning an oscillator using an external stable oscillating source as a reference. Calibration logic is included to compare a signal from the local oscillator to the reference signal and vary the local signal to a desired frequency. In one embodiment, a binary search algorithm is used to tune the local oscillator. The local oscillating signal can be sent to one or more circuits including at least one sensor of a touch sensitive panel for detecting touch events.

A circuitry for measuring a time interval with ring oscillator has a ring oscillator formed by a plurality of delay switching units, a counter and an encoder. Wherein, the ring oscillator generates a plurality of oscillating signals when receives a pulse signal used to turn on or turn off the ring oscillator. The counter can count the numbers of the oscillating signal during an active period of the pulse signal to generate a counting value. In addition, the encoder encodes the oscillation signals generated by a plurality of delay switching unit with a certain interval of delay time. Therefore, when the pulse signal is disabled to lead to turn off the ring oscillator, one can obtain the time interval of the pulse signal based on the encode data and the counting value.

A plurality of inverters are arranged serially to form a ring oscillator and coupled to receive a reference clock signal. The reference clock signal is used to switch the inverters on and off so that not all of the inverters are on at a same time. The ring oscillator circuit is used as a divider circuit to divide the frequency of the reference clock signal to produce a local oscillator signal at a second frequency.

A quadrature LC tank based digitally controlled ring oscillator (DCO). The oscillator structure incorporates a plurality of stages, each stage including a buffer and a series LC tank. Four stages are coupled together to create a 360 degree phase shift around a loop. The oscillation frequency of the oscillator is the same as the resonant frequency of each LC tank, therefore it avoids quality factor degradation of LC tanks found in the prior art. In one example embodiment, class-D amplifiers are used to drive each of the LC tanks Capacitor banks before at the input and output of the buffers provide coarse and fine tuning of the frequency of oscillation. The high efficiency exhibited by these amplifiers results in very good phase noise performance of this oscillator. The oscillator utilizes a startup circuit to launch oscillation upon power on.

A synchronous mirror delay (300) includes a ring oscillator that generates a plurality of tap clock signals (T1-T7) with one tap clock signal being designated an oscillator clock signal. In response to an input clock signal, a model delay line generates a model delayed clock signal having a model delay relative to the input clock signal. A coarse delay circuit generates a coarse delay count (316) responsive to the oscillator, input, and model delayed clock signals, and activates a coarse delay enable signal responsive to the delay count being equal to a reference count value. A fine delay circuit latches the tap clock signals and develops a fine delay from the latched signals, and activates a fine delay enable signal having the fine delay in response to the coarse delay enable signal. An output circuit generates a delayed clock signal responsive to the coarse and fine delay enable signals going active.