133 results about "Bit manipulation" patented technology

The present invention provides an adaptive computing engine (ACE) that includes processing nodes having different capabilities such as arithmetic nodes, bit-manipulation nodes, finite state machine nodes, input / output nodes and a programmable scalar node (PSN). In accordance with one embodiment of the present invention, a common architecture is adaptable to function in either a kernel node, or k-node, or as general purpose RISC node. The k-node acts as a system controller responsible for adapting other nodes to perform selected functions. As a RISC node, the PSN is configured to perform computationally intensive applications such as signal processing. The present invention further provides an interconnection scheme so that a plurality of ACE devices operates under the control of a single k-node.

Techniques are provided for generating a hash value for searching for substrings in a data stream without reading more than one element (e.g. one byte) at a time. According to one technique, a before a next element is added to an old hash value, the old hash value is circularly shifted one or more bits. The first original element is shifted a number of bits and XOR'ed against the old hash value. The next element is added to the old hash value. In one embodiment, an entry value is retrieved for each element from an index table and the XOR and shift operations are performed on the entry values. According to another technique, each Linear Feedback Shift Register (LFSR) of a plurality of LFSRs read in one element at a time beginning at different offsets. Each LFSR uses the same state machine. The result of reading a number of elements into an LFSR is used as the hash value.

The invention discloses a system and method for realizing parallel decompression of hardware. The system comprises a variable-length bit manipulation module, a Huffman table recovery module, a Huffman coding module and a decoding module, wherein the variable-length bit manipulation module is used for carrying out variable-length bit manipulation on to-be-decompressed data to acquire variable-length data; the Huffman table recovery module is used for recovering a Huffman table in accordance with the variable-length data; the Huffman coding module is used for executing Huffman coding in parallel in accordance with the Huffman table; and the decoding module is used for carrying out decoding in accordance with the Huffman coding result. According to the system and method for realizing the parallel decompression of hardware, an FPGA (field programmable gate array) is utilized to realize a Gzip decompressing function, a parallel decompression algorithm is utilized and a hardware circuit structure suitable for the algorithm is designed, thus improving the processing efficiency of the decompression greatly.

A bit vector array apparatus provides a high speed method for processing network transmission controls. Complex data structures for controlling network access are represented in the simplest possible form as single bit vector elements. The bit vector elements are combined into bit vectors comprised of 32 single bit vector elements. The bit vectors are processed in parallel in the bit vector array apparatus, which is comprised of special-purpose bit manipulation functions to expedite the processing.

The invention relates to image decomposition strategies and computer-based methods for implementing them. In one method of the invention, the ordering of tetrahedral shapes that define or approximate an image is performed in such a way that neighboring tetrahedral shapes can be identified, located and efficiently used. In one aspect, binary location code array is used to represent an image and the method for identify the neighbor shape employs a bit manipulation step in code or psuedo-code for operating a computer. In this aspect, the invention allows one to move between adjacent tetrahedra, and any data corresponding to the tetrahedra, in constant time.

The invention discloses an adder device, a data accumulation method, and a data processing device. The adder device comprises a first adder module which is provided with an addition tree unit composed of a multi-stage adder array, and also provided with a first control unit, wherein the addition tree unit accumulates the data in a mode of step-by-step accumulation based on a control signal of the first control unit; a second adder module which comprises two input addition and subtraction operation units and a second control unit, and is used for the addition or subtraction operation of the input data; a shift operation module which is used for the left shift operation of the output data of the first adder module; an AND operation module which is used for the AND operation of the output data of the shift operation module and the output data of the second adder module; and a controller module which is used for controlling the data input of the first and second adder modules, controlling the shift operation of the shift operation module, and controlling the transmission of control signals of the first and second control units. Therefore, the adder device achieves the quick accumulation of data.

Microprocessor shifter circuits utilizing butterfly and inverse butterfly circuits, and control circuits therefor, are provided. The same shifter circuits can also perform complex bit manipulations at high speeds, including butterfly and inverse butterfly operations, parallel extract and deposit operations, group operations, mix operations, permutation operations, as well as instructions executed by existing microprocessors, including shift right, shift left, rotate, extract, deposit and multimedia mix operations. The shifter circuits can be provided in various combinations to provide microprocessor functional units which perform a plurality of bit manipulation operations.