The invention provides novel
system architecture of a navigation
radio frequency (RF)
receiver with low
power consumption. The
system architecture comprises a first down converter and two orthogonal second down
converters and also comprises a divide-by-2 divider of a
frequency synthesizer, wherein the first down converter and the two orthogonal second down
converters are arranged in a
signal channel in sequence and are used for carrying out twice
down conversion on the RF signals received by the
signal channel; and the divide-by-2 divider is arranged in a same sub-
chip together with the first and second down
converters, directly outputs the output frequency of a
voltage-controlled oscillator to the first down converter and outputs the output frequency of the
voltage-controlled oscillator to the second down converters after dividing the output frequency by 2. The
system architecture has the following advantages: the system architecture is optimized and improved and the design requirements of a plurality of submodules such as an
intermediate frequency (IF) filter, a prescaler and the like for subsequent
signal processing are simplified through twice IF conversion, thus using a single submodule with lower
power consumption to achieve the aim of reducing the
power consumption of the whole navigation
chip while realizing the receiving function of the navigation
chip towards the RF signals.