62results about How to "Reduce impedance difference" patented technology

The invention relates to a display device and an adjusting method thereof. The display device comprises a display panel and a driving module. The display panel comprises a display area and a fan-out area. A plurality of data lines are arranged in the display area and a plurality of connecting lines are arranged in the fan-out area. The driving module comprises a detection unit for detecting the resistance value of the connecting line. The connecting line comprises a first connecting line and a second connecting line; a plurality of source driving units, wherein the source driving units are internally integrated with adjustable resistors; and a control chip electrically connected with a plurality of source driving units through function pins, wherein the control chip is used for comparing the resistance values of the first connection line and the second connection line, and outputting a control signal according to the resistance value comparison result. The source driving unit receivesthe control signal, and adjusts the resistance value of the adjustable resistor according to the control signal, so that the resistance value of the first connection line and the second connection line in the fan-out region is the same.

The invention discloses a special-shaped display panel and a display device. A display area including a first display area, a second display area, and a third display area; A plurality of display pixels located in the display area; A signal line extending in a first direction, comprising a first signal line, a second signal line and a third signal line, the three signal lines driving display pixels in three display regions, respectively, and the third signal line comprising a third signal line A and a third signal line B; A signal connection line connected to the first signal line and the third signal line A respectively; A resistance-capacitance balancing module which constitutes a capacitance with the signal line or is connected with the signal line to increase the impedance on the signal line, wherein at least any one of the second signal line and the third signal line B is provided with a resistance-capacitance balancing module. By the invention, the impedance difference between different signal lines on the display panel can be reduced, and the display effect can be improved.

A touch panel having a touch sensing region and at least two connection regions around the touch sensing region is provided. The touch panel includes first conductive patterns, second conductive patterns, pads, and signal transmission lines. The first and second conductive patterns are disposed in the touch sensing region. Each first conductive pattern has a first end and an opposite second end. Each second conductive pattern has a third end and an opposite fourth end. The pads are respectively disposed in the connection regions. The first, second, third, and fourth ends are electrically connected to the pads in the corresponding connection region respectively through the signal transmission lines so that the distance from each first end, each second end, each third end, and each fourth end to the corresponding connection region is not greater than the distance from those to the other connection region.

The invention discloses a technique for designing the power layout of an integrated circuit. The power layout design forms a power mesh and a power ring with a plurality of metal trunks with uniform line width. In particular, the power ring includes a plurality of metal rings, which are formed by arranging denser layout of the metal trunks with uniform line width. The power ring serves as a function of receiving and providing a power source to the elements of the integrated circuit.

The invention provides an array substrate and a display panel. The array substrate comprises a display area and a non-display area. The array substrate comprises a first metal layer, a second metal layer, a drive chip and a third metal layer, wherein a plurality of gate lines are formed inside the display area on the first metal layer and the second metal layer, the first metal layer and / or the second metal layer extend / extends to the non-display area from the display area, and a plurality of first signal connecting lines are formed inside the non-display area; the drive chip is positioned inside the non-display area; a plurality of data lines are formed inside the display area on the third metal layer, a plurality of second signal connecting lines are formed on the third metal layer, eachsecond signal connecting line is led out from the drive chip, and each second signal connecting line is electrically connected with one corresponding first signal connecting line extending to the non-display area from the display area respectively so as to form a signal transmission line, the electrical resistivity of the third meta layer is smaller than that of the first metal layer and that ofthe second metal layer, and the difference value of impedance among the signal transmission lines is smaller than a preset threshold value. According to the array substrate and the display panel provided by the invention, the display effect is improved.

The invention provides ultrasonic diagnostic equipment and an ultrasonic imaging method. By obtaining first array element sensitivity or impedance, second array element sensitivity or impedance is acquired; according to the first array element sensitivity or impedance, a first compensation coefficient is determined, and according to the second array element sensitivity or impedance, a second compensation coefficient is determined, wherein the first compensation coefficient is different from the second compensation coefficient; compensation processing is carried out on a first echo signal according to the first compensation coefficient, and compensation processing is carried out on a second echo signal according to the second compensation coefficient; and the first eco signal and the secondeco signal after compensation treatment are subjected to beam synthesis, and are processed to generate an ultrasonic image. Corresponding compensation coefficients are determined according to the sensitivity or impedance of the respective array elements, then the eco signals generated by the respective array elements are compensated to reduce sensitivity or impedance difference between differentarray elements, and space consistency and uniformity of images are improved, thereby improving the final ultrasonic image display effect.

A circuit board is provided for improving signal quality, including a signal plane for a plurality of signal traces arranged thereon and a ground plane formed by a plurality of tiles connected to each other in an array. Each tile is formed by ground traces. Different line segments of a signal trace mapped on the ground plane cross ground traces of the tiles at similar angles, thereby minimizing interaction between the ground traces and the signal traces to reduce differences in impedances of the signal traces.

Scan lines and data lines are disposed in a display region of a substrate, and multiple pixel regions are divided thereon. Switch components are disposed in the pixel regions, and each switch component is electrically connected to the scan line and data line. Pixel electrodes are disposed in the pixel regions and each pixel electrode is electrically connected to the switch component. Wires are disposed in a non-display region of the substrate, and at least one portion of each wire includes a first and a second conductor layer, wherein the second conductor layer is disposed on the first conductor layer and parallel-connected to the first conductor layer. The first conductor layer and one of the scan lines, data lines, and the pixel electrodes are in the same layer. The second conductor layer and another one of the scan lines, data lines, and the pixel electrodes are in the same layer.

There is provided an antenna small in its size but capable of achieving sufficient gain. The antenna comprises antenna elements connected to a power source. The antenna elements comprise upstanding vertical sections connected to the power source and horizontal sections substantially parallel with a ground pattern and having one end thereof connected to an end portion of the vertical sections. The antenna elements further comprise short stubs provided away from the vertical sections toward the other end of the horizontal sections and connected to the ground pattern, and open-ended open stubs provided away from the short stubs toward the other end of the horizontal sections and extending from the horizontal sections toward the ground pattern. The antenna elements are made of a metal foil and are provided on an antenna board.

The present invention provides a stimulation electrode structure for an artificial retina. The structure comprises an insulating substrate which is formed by a flexible material with biological compatibility, and a plurality of stimulation electrodes which are arranged in the insulating substrate and form an array body which is arranged along a two-dimensional direction parallel to the insulating substrate. The stimulation electrodes protrude from the surface of the insulating substrate. Each of the stimulation electrodes comprises a base section and an exposed section. The electrode height of each stimulation electrode is equal to a sum of the height of the base section and the height of the exposed section, the heights of the stimulation electrodes are roughly the same, and the exposed sections of the stimulation electrodes are gradually reduced from the center of the array body to the edge of the array body. In the electrode array of the artificial retina in the invention, the array body formed by three dimensions of stimulation electrodes, at the same time the impedance difference between the stimulation electrodes is reduced, and thus the retina can be more effectively stimulated.

The invention relates to an array substrate, a display panel and a vertical light line repair method for the display panel. The array substrate is divided into a display region and a non-display region and comprises gate lines, data lines, a terminal region and a fan out region, wherein the gate lines and the data lines are arranged in the display region; the terminal region is arranged in the non-display region; a driving chip is arranged in the terminal region; the fan out region is arranged in the non-display region; at least one pair of fan out routes which are consistent in route shape and are configured in parallel up and down are arranged in the fan out region; the fan out routes include a first fan out route and a second fan out route; the first fan out route is isolated from the second fan out route by an insulation layer; the insulation layer is provided with at least one via hole; and the first fan out route and the second fan out route are connected and conducted mutually through the via hole. The impedance difference can be greatly reduced, a vertical light line caused by breakage of the first fan out route or the second fan out route is improved, and an occurrence rate of the vertical light line is reduced.

A display panel and an electronic device is provided. A voltage drop value of the clock input transistor of a pull-up module of m1st GOA unit connected to an n1st clock signal line is greater than a voltage drop value of the clock input transistor of a pull-up module of m2nd GOA unit connected to the n2nd clock signal line. Based on this circuit structure, a CK impedance difference existing in 8K ultra-high resolution electronic devices can be alleviated.

A display panel and an electronic device is provided. A voltage drop value of the clock input transistor of a pull-up module of m1st GOA unit connected to an n1st clock signal line is greater than a voltage drop value of the clock input transistor of a pull-up module of m2nd GOA unit connected to the n2nd clock signal line. Based on this circuit structure, a CK impedance difference existing in 8K ultra-high resolution electronic devices can be alleviated.

The invention provides a side-by-side cable which comprises at least two conductors and insulating layers respectively coating each conductor, wherein the conductors and the insulating layers form a wire; two wires are arranged side by side and then are coated by one coating layer; and the coating layer is coated on the outer layers of the two wires which are arranged side by side by adopting a polyester tape; and the insulating layers are dielectric media by which the cables are insulated; each conductor is further coated by the insulating layer through an Teflon wire; the coating layer further comprises a copper foil which is coated on the outer layer of the wire; and the polyester tape is coated on the outer layer of the copper foil. Compared with general twisted pair cables, the side-by-side cable disclosed by the invention is more stable in performance and smaller in impedance difference and delay difference.