1072results about How to "Avoid switching" patented technology

The present invention relates to the design of an essentially digital system. As one example of digital systems, these may perform real-time transformations on time discrete digitized samples of analogue quantities. An example of such a system is a digital communication system. The transformations on the data can be specified in a programming language and executed on a processor such as a programmable processor or directly on application specific hardware. In accordance with the present invention the digital system is described as a set of threads in a description language. Alternative names for a thread are tasks and processes. The set of threads defines a representation or model of the digital system. In accordance with the present invention, the representation or model is preferably executable at each stage of the design independent of the current level of abstraction of that representation or model. With description language is meant a programming language. In accordance with the present invention each of the threads has a variable having an assignable value which represents the “local time” of said thread, i.e. a time associated only with that thread, which can be used for sequencing the processing of that thread with respect to other threads. With the word “local” is meant that the time is an attribute of the thread only. In accordance with the present invention a means is provided for the designer to assign a delay to each thread or operation within a thread, this delay representing for instance the processing time for the respective operation or thread on a processing engine, e.g. a computer. By this means, not only can the processing of threads be scheduled but also the designer may assign a value representative of an elapsed time for the processing of a thread or operation on a processing engine. In addition, the threads may be refined concurrently, while still keeping their local time so that after the refining process the new representation of the digital system is executable, i.e. the processing of the refined threads can be scheduled without divergence from the specification.

A multiple phase cell dispatch scheme, in which each phase uses a simple and fair (e.g., round robin) arbitration methods, is described. VOQs of an input module and outgoing links of the input module are matched in a first phase. An outgoing link of an input module is matched with an outgoing link of a central module in a second phase. The arbiters become desynchronized under stable conditions which contributes to the switch's high throughput characteristic. Using this dispatch scheme, a scalable multiple-stage switch able to operate at high throughput, without needing to resort to speeding up the switching fabric and without needing to use buffers in the second stage, is possible. The cost of speed-up and the cell out-of-sequence problems that may occur when buffers are used in the second stage are therefore avoided.

A method for measuring a neural response to a stimulus. Measurement circuitry is settled prior to a stimulus, by connecting a sense electrode to the measurement circuitry to allow the measurement circuitry to settle towards a bio-electrically defined steady state. Charge is recovered on stimulus electrodes by short circuiting the stimulus electrodes to each other. An electrical stimulus is then applied from the stimulus electrodes to neural tissue, while keeping the sense electrode disconnected from the measurement circuitry. After the stimulus, a delay is imposed during which the stimulus electrodes are open circuited and the sense electrode is disconnected from the measurement circuitry and from the stimulus electrodes. After the delay, a neural response signal present at the sense electrode is measured by connecting the sense electrode to the measurement circuitry.

A charge pump DC / DC converter circuit of the present invention includes: a monitor circuit that detects a potential difference between terminals of a semiconductor switch that turns on during a first period, so as to output a determining signal corresponding to the potential difference; and each of drive circuits that outputs a drive signal to a semiconductor switch that turns on during a first period, in response to the determining signal. The drive signal increases the on-resistance of the semiconductor switch in proportion to the detected potential difference.

A driver drill that can effectively prevent erroneous clutch operation in a drill mode is provided. A flat washer positioned between steel balls for locking an internal gear and a coil spring is rotatable by rotative operation of a mode-change ring. Also, protruding streaks are provided on a small-diameter unit of a second gear case around which a flat washer is externally mounted. The protruding streaks interfere with internal projections on an inner circumference of the flat washer at its predetermined rotating position to regulate a forward movement of the flat washer. When a drill mode is selected with the mode-change ring, the flat washer is locked by the protruding streaks.

An implantable device for controlling electrical conditions of body tissue. A feedback sense electrode and a compensation electrode are positioned proximal to the tissue to make electrical contact with the tissue. A feedback amplifier is referenced to ground, and takes as an input a feedback signal from the feedback sense electrode. The output of the feedback amplifier is connected to the compensation electrode. The feedback amplifier thus drives the neural tissue via the compensation electrode in a feedback arrangement which seeks to drive the feedback signal to ground, or other desired electrical value.

A pipeline-based matching scheduling approach for input-buffered switches relaxes the timing constraint for arbitration with matching schemes, such as CRRD and CMSD. In the new approach, arbitration may operate in a pipelined manner. Each sub-scheduler is allowed to take more than one time slot for its matching. Every time slot, one of them provides a matching result(s). The sub-scheduler can use a matching scheme such as CRRD and CMSD.

In an electric power storage system according to the present invention, in the case of charging, a plurality of capacitors of each circuit block of the electric power storage system are switched to a serial connection to initiate the charging. When the output voltage of power storage means reaches the maximum input voltage of DC-AC conversion means, each capacitor of a number j of circuit blocks is switched to a parallel connection in order of higher block voltage. Also up to the time when the maximum input voltage is reached again, each capacitor of a number j of circuit blocks is switched to a parallel connection in order of higher block voltage. In the case of discharging, pluralities of capacitors of each circuit block of the electric power storage system are switched to a parallel connection to initiate the discharging. When the output voltage of power storage means reaches the minimum input voltage of DC-AC conversion means, each capacitor of a number k of circuit blocks is switched to a serial connection in order of higher block voltage. Also up to the time when the minimum input voltage is reached gain, each capacitor of a number k of circuit blocks is switched to a serial connection in order of higher block voltage. Accordingly, the electric power storage system is hardly affected by the capacitance error of the capacitors, and charging / discharging efficiency can be improved.

A hybrid multi-bit memory device may include a plurality of unit cells arranged in a matrix of a plurality of rows and columns. Each of the unit cells may include a first memory unit and a second memory unit. The first and second memory unit may share a source and a drain. The first memory unit of each unit cell arranged in each row may be connected to one of a plurality of word lines, and the drain of each unit cell arranged in each column may be connected to one of a plurality of bit lines.